A
80960JD
Table 6. 132-Lead PGA Pinout — In Signal Order
Signal
A2
Pin
C5
Signal
AD31
ADS
Pin
K3
Signal
TDI
Pin
D12
B4
Signal
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
W/R
Pin
B9
A3
C4
A1
TDO
TMS
TRST
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCPLL
VSS
D2
AD0
M14
L13
K12
N14
M13
L12
P14
N13
M12
M11
N12
P13
M10
P12
M9
ALE
G3
A3
A14
C12
A6
D13
E2
AD1
ALE
AD2
BE0
H3
E13
F2
AD3
BE1
J3
A7
AD4
BE2
L1
A8
F13
G2
AD5
BE3
L2
A9
AD6
BLAST
BSTAT
CLKIN
D/C
C3
D1
G13
H2
AD7
F3
D14
E1
AD8
H14
B2
H13
J2
AD9
E14
F1
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
DEN
E3
J13
K2
DT/R
FAIL
D3
F14
G1
G14
H1
C6
K13
N5
HOLD
HOLDA
LOCK/ONCE
NC
C9
C2
N6
M8
C1
J1
N7
M7
A4
J14
K1
N8
M6
NC
A5
N9
P4
NC
B5
K14
L14
P5
N10
N11
B1
P3
NC
B14
C7
N4
NC
M5
NC
C8
P6
WIDTH/HLTD0
WIDTH/HLTD1
XINT0
B3
P2
NC
C14
G12
J12
M3
A10
F12
E12
C13
B13
P7
A2
M4
NC
P8
C11
C10
A13
B12
B11
A12
B10
A11
N3
NC
P9
XINT1
P1
NC
P10
P11
H12
B6
XINT2
N2
NMI
XINT3
N1
RDYRCV
RESET
STEST
TCK
XINT4
L3
XINT5
M2
VSS
B7
XINT6
M1
VSS
B8
XINT7
NOTE: Do not connect any external logic to pins marked NC (no connect pins).
15
PRELIMINARY
INTEL [ INTEL ]
