8088
Certain locations in memory are reserved for specific
CPU operations (See Figure 4). Locations from ad-
dresses FFFF0H through FFFFFH are reserved for
operations including a jump to the initial system ini-
tialization routine. Following RESET, the CPU will al-
ways begin execution at location FFFF0H where the
jump must be located. Locations 00000H through
003FFH are reserved for interrupt operations. Four-
byte pointers consisting of a 16-bit segment address
and a 16-bit offset address direct program flow to
one of the 256 possible interrupt service routines.
The pointer elements are assumed to have been
stored at their respective places in reserved memory
prior to the occurrence of interrupts.
figuration. The definition of a certain subset of the
pins changes, dependent on the condition of the
strap pin. When the MN/MX pin is strapped to GND,
the 8088 defines pins 24 through 31 and 34 in maxi-
mum mode. When the MN/MX pin is strapped to
V , the 8088 generates bus control signals itself on
CC
pins 24 through 31 and 34.
The minimum mode 8088 can be used with either a
multiplexed or demultiplexed bus. The multiplexed
bus configuration is compatible with the MCS-85
multiplexed bus peripherals. This configuration (See
Figure 5) provides the user with a minimum chip
count system. This architecture provides the 8088
processing power in a highly integrated form.
The demultiplexed mode requires one latch (for 64K
addressability) or two latches (for a full megabyte of
addressing). A third latch can be used for buffering if
the address bus loading requires it. A transceiver
can also be used if data bus buffering is required
(See Figure 6). The 8088 provides DEN and DT/R to
control the transceiver, and ALE to latch the ad-
dresses. This configuration of the minimum mode
provides the standard demultiplexed bus structure
with heavy bus buffering and relaxed bus timing re-
quirements.
Minimum and Maximum Modes
The requirements for supporting minimum and maxi-
mum 8088 systems are sufficiently different that
they cannot be done efficiently with 40 uniquely de-
fined pins. Consequently, the 8088 is equipped with
a strap pin (MN/MX) which defines the system con-
The maximum mode employs the 8288 bus control-
ler (See Figure 7). The 8288 decodes status lines
S0, S1, and S2, and provides the system with all bus
control signals. Moving the bus control to the 8288
provides better source and sink current capability to
the control lines, and frees the 8088 pins for extend-
ed large system features. Hardware lock, queue
status, and two request/grant interfaces are provid-
ed by the 8088 in maximum mode. These features
allow co-processors in local bus and remote bus
configurations.
231456–4
Figure 4. Reserved Memory Locations
7
INTEL [ INTEL ]
