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8088 参数 Datasheet PDF下载

8088图片预览
型号: 8088
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微处理器HMOS [8-BIT HMOS MICROPROCESSOR]
分类和应用: 微处理器
文件页数/大小: 30 页 / 380 K
品牌: INTEL [ INTEL ]
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8088  
Table 1. Pin Description (Continued)  
Name and Function  
Symbol  
Pin No.  
Type  
NMI  
17  
I
NON-MASKABLE INTERRUPT: is an edge triggered input which causes a  
type 2 interrupt. A subroutine is vectored to via an interrupt vector lookup  
table located in system memory. NMI is not maskable internally by  
software. A transition from a LOW to HIGH initiates the interrupt at the end  
of the current instruction. This input is internally synchronized.  
RESET  
CLK  
21  
19  
I
I
RESET: causes the processor to immediately terminate its present activity.  
The signal must be active HIGH for at least four clock cycles. It restarts  
execution, as described in the instruction set description, when RESET  
returns LOW. RESET is internally synchronized.  
CLOCK: provides the basic timing for the processor and bus controller. It is  
asymmetric with a 33% duty cycle to provide optimized internal timing.  
a
g
: is the 5V 10% power supply pin.  
CC  
V
40  
1, 20  
33  
V
CC  
GND  
GND: are the ground pins.  
MN/MX  
I
MINIMUM/MAXIMUM: indicates what mode the processor is to operate in.  
The two modes are discussed in the following sections.  
e
functions which are unique to minimum mode are described; all other pin functions are as described above.  
The following pin function descriptions are for the 8088 minimum mode (i.e., MN/MX  
V
). Only the pin  
CC  
Symbol Pin No. Type  
Name and Function  
IO/M  
28  
O
STATUS LINE: is an inverted maximum mode S2. It is used to distinguish a  
memory access from an I/O access. IO/M becomes valid in the T4 preceding a  
e
e
bus cycle and remains valid until the final T4 of the cycle (I/O  
LOW). IO/M floats to 3-state OFF in local bus ‘‘hold acknowledge’’.  
HIGH, M  
WR  
29  
O
WRITE: strobe indicates that the processor is performing a write memory or write  
I/O cycle, depending on the state of the IO/M signal. WR is active for T2, T3, and  
Tw of any write cycle. It is active LOW, and floats to 3-state OFF in local bus  
‘‘hold acknowledge’’.  
INTA  
ALE  
24  
25  
O
O
INTA: is used as a read strobe for interrupt acknowledge cycles. It is active LOW  
during T2, T3, and Tw of each interrupt acknowledge cycle.  
ADDRESS LATCH ENABLE: is provided by the processor to latch the address  
into an address latch. It is a HIGH pulse active during clock low of T1 of any bus  
cycle. Note that ALE is never floated.  
DT/R  
DEN  
27  
26  
O
O
DATA TRANSMIT/RECEIVE: is needed in a minimum system that desires to use  
a data bus transceiver. It is used to control the direction of data flow through the  
transceiver. Logically, DT/R is equivalent to S1 in the maximum mode, and its  
e
3-state OFF in local ‘‘hold acknowledge’’.  
e
timing is the same as for IO/M (T  
HIGH, R  
LOW). This signal floats to  
DATA ENABLE: is provided as an output enable for the data bus transceiver in a  
minimum system which uses the transceiver. DEN is active LOW during each  
memory and I/O access, and for INTA cycles. For a read or INTA cycle, it is  
active from the middle of T2 until the middle of T4, while for a write cycle, it is  
active from the beginning of T2 until the middle of T4. DEN floats to 3-state OFF  
during local bus ‘‘hold acknowledge’’.  
3