欢迎访问ic37.com |
会员登录 免费注册
发布采购

8088 参数 Datasheet PDF下载

8088图片预览
型号: 8088
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微处理器HMOS [8-BIT HMOS MICROPROCESSOR]
分类和应用: 微处理器
文件页数/大小: 30 页 / 380 K
品牌: INTEL [ INTEL ]
 浏览型号8088的Datasheet PDF文件第1页浏览型号8088的Datasheet PDF文件第2页浏览型号8088的Datasheet PDF文件第3页浏览型号8088的Datasheet PDF文件第5页浏览型号8088的Datasheet PDF文件第6页浏览型号8088的Datasheet PDF文件第7页浏览型号8088的Datasheet PDF文件第8页浏览型号8088的Datasheet PDF文件第9页  
8088  
Table 1. Pin Description (Continued)  
Symbol Pin No. Type  
Name and Function  
HOLD,  
HLDA  
31, 30  
I, O HOLD: indicates that another master is requesting a local bus ‘‘hold’’. To be  
acknowledged, HOLD must be active HIGH. The processor receiving the ‘‘hold’’  
request will issue HLDA (HIGH) as an acknowledgement, in the middle of a T4 or  
Ti clock cycle. Simultaneous with the issuance of HLDA the processor will float  
the local bus and control lines. After HOLD is detected as being LOW, the  
processor lowers HLDA, and when the processor needs to run another cycle, it  
will again drive the local bus and control lines. HOLD and HLDA have internal  
pull-up resistors.  
Hold is not an asynchronous input. External synchronization should be provided if  
the system cannot otherwise guarantee the set up time.  
SSO  
34  
O
STATUS LINE: is logically equivalent to SO in the maximum mode. The  
combination of SSO, IO/M and DT/R allows the system to completely decode the  
current bus cycle status.  
IO/M  
DT/R  
SSO  
Characteristics  
1(HIGH)  
1
1
1
0(LOW)  
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Interrupt Acknowledge  
Read I/O Port  
Write I/O Port  
Halt  
Code Access  
Read Memory  
Write Memory  
Passive  
e
The following pin function descriptions are for the 8088/8288 system in maximum mode (i.e., MN/MX  
GND). Only the pin functions which are unique to maximum mode are described; all other pin functions are as  
described above.  
Symbol Pin No. Type  
S2, S1, S0 2628  
Name and Function  
O
STATUS: is active during clock high of T4, T1, and T2, and is returned to the  
passive state (1,1,1) during T3 or during Tw when READY is HIGH. This status is  
used by the 8288 bus controller to generate all memory and I/O access control  
signals. Any change by S2, S1, or S0 during T4 is used to indicate the beginning  
of a bus cycle, and the return to the passive state in T3 and Tw is used to  
indicate the end of a bus cycle.  
These signals float to 3-state OFF during ‘‘hold acknowledge’’. During the first  
clock cycle after RESET becomes active, these signals are active HIGH. After  
this first clock, they float to 3-state OFF.  
S2  
S1  
S0  
Characteristics  
0(LOW)  
0
0
0
1(HIGH)  
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Interrupt Acknowledge  
Read I/O Port  
Write I/O Port  
Halt  
Code Access  
Read Memory  
Write Memory  
Passive  
4