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8088 参数 Datasheet PDF下载

8088图片预览
型号: 8088
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微处理器HMOS [8-BIT HMOS MICROPROCESSOR]
分类和应用: 微处理器
文件页数/大小: 30 页 / 380 K
品牌: INTEL [ INTEL ]
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8088  
id throughout each bus cycle. In addition, the bus  
can be demultiplexed at the processor with a single  
address latch if a standard, non-multiplexed bus is  
desired for the system.  
Bus Operation  
The 8088 address/data bus is broken into three  
partsÐthe lower eight address/data bits (AD0–  
AD7), the middle eight address bits (A8A15), and  
the upper four address bits (A16A19). The ad-  
dress/data bits and the highest four address bits are  
time multiplexed. This technique provides the most  
efficient use of pins on the processor, permitting the  
use of a standard 40 lead package. The middle eight  
address bits are not multiplexed, i.e. they remain val-  
Each processor bus cycle consists of at least four  
CLK cycles. These are referred to as T1, T2, T3, and  
T4 (See Figure 8). The address is emitted from the  
processor during T1 and data transfer occurs on the  
bus during T3 and T4. T2 is used primarily for chang-  
231456–8  
Figure 8. Basic System Timing  
10