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8088 参数 Datasheet PDF下载

8088图片预览
型号: 8088
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微处理器HMOS [8-BIT HMOS MICROPROCESSOR]
分类和应用: 微处理器
文件页数/大小: 30 页 / 380 K
品牌: INTEL [ INTEL ]
 浏览型号8088的Datasheet PDF文件第18页浏览型号8088的Datasheet PDF文件第19页浏览型号8088的Datasheet PDF文件第20页浏览型号8088的Datasheet PDF文件第21页浏览型号8088的Datasheet PDF文件第23页浏览型号8088的Datasheet PDF文件第24页浏览型号8088的Datasheet PDF文件第25页浏览型号8088的Datasheet PDF文件第26页  
8088  
A.C. CHARACTERISTICS (Continued)  
TIMING RESPONSES  
8088  
Min  
8088-2  
Min  
Test  
Conditions  
Symbol  
Parameter  
Units  
Max  
Max  
TCLML  
Command Active Delay  
(Note 1)  
10  
35  
10  
35  
ns  
TCLMH Command Inactive Delay  
(Note 1)  
10  
35  
10  
35  
65  
ns  
ns  
TRYHSH READY Active to  
Status Passive (Note 3)  
110  
TCHSV Status Active Delay  
10  
10  
110  
130  
110  
10  
10  
60  
70  
60  
ns  
ns  
ns  
ns  
ns  
ns  
TCLSH  
TCLAV  
TCLAX  
TCLAZ  
TSVLH  
Status Inactive Delay  
Address Valid Delay  
Address Hold Time  
Address Float Delay  
10  
10  
10  
10  
TCLAX  
80  
15  
TCLAX  
50  
15  
Status Valid to ALE High  
(Note 1)  
TSVMCH Status Valid to MCE High  
(Note 1)  
15  
15  
15  
15  
ns  
ns  
TCLLH  
CLK Low to ALE Valid  
(Note 1)  
TCLMCH CLK Low to MCE (Note 1)  
TCHLL ALE Inactive Delay (Note 1)  
TCLMCL MCE Inactive Delay (Note 1)  
TCLDV Data Valid Delay  
15  
15  
15  
15  
15  
60  
ns  
ns  
ns  
ns  
ns  
ns  
15  
10  
10  
5
110  
10  
10  
5
TCHDX Data Hold Time  
e
C
20100 pF for  
L
TCVNV Control Active Delay  
(Note 1)  
45  
45  
45  
45  
All 8088 Outputs  
in Addition to  
Internal Loads  
TCVNX Control Inactive Delay  
(Note 1)  
10  
0
10  
0
ns  
ns  
TAZRL  
Address Float to  
Read Active  
TCLRL  
TCLRH  
RD Active Delay  
RD Inactive Delay  
10  
10  
165  
150  
10  
10  
100 ns  
80  
ns  
ns  
b
TCLCL 45  
b
TCLCL 40  
TRHAV RD Inactive to Next  
Address Active  
TCHDTL Direction Control  
Active Delay (Note 1)  
50  
30  
50  
30  
ns  
ns  
TCHDTH Direction Control  
Inactive Delay (Note 1)  
TCLGL  
GT Active Delay  
85  
85  
50  
50  
ns  
ns  
ns  
TCLGH GT Inactive Delay  
TRLRH RD Width  
b
2TCLCL 75  
b
2TCLCL 50  
TOLOH Output Rise Time  
TOHOL Output Fall Time  
20  
12  
20  
12  
ns From 0.8V to 2.0V  
ns From 2.0V to 0.8V  
NOTES:  
1. Signal at 8284 or 8288 shown for reference only.  
2. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.  
3. Applies only to T3 and wait states.  
4. Applies only to T2 state (8 ns into T3 state).  
22  
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