8088
WAVEFORMS (Continued)
BUS TIMINGÐMAXIMUM MODE SYSTEM (USING 8288)
NOTES:
1. All signals switch between V
231456–16
and V unless otherwise specified.
OL
OH
2. RDY is sampled near the end of T , T , T to determine if T machines states are to be inserted.
3. Cascade address is valid between first and second INTA cycles.
2
3
w
w
4. Two INTA cycles run back-to-back. The 8088 local ADDR/DATA bus is floating during both INTA cycles. Control for
pointer address is shown for second INTA cycle.
5. Signals at 8284 or 8288 are shown for reference only.
6. The issuance of the 8288 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA and
DEN) lags the active high 8288 CEN.
7. All timing measurements are made at 1.5V unless otherwise noted.
8. Status inactive in state just prior to T .
4
24
INTEL [ INTEL ]
