8088
A.C. CHARACTERISTICS (Continued)
TIMING RESPONSES
8088
Min
8088-2
Min
Test
Symbol
Parameter
Units
Conditions
Max
Max
TCLAV
TCLAX
TCLAZ
TLHLL
TCLLH
TCHLL
TLLAX
Address Valid Delay
Address Hold Time
Address Float Delay
ALE Width
10
10
110
10
10
60
ns
ns
ns
ns
ns
ns
ns
TCLAX
80
TCLAX
50
b
TCLCH 20
b
TCLCH 10
ALE Active Delay
ALE Inactive Delay
80
85
50
55
b
TCHCL 10
b
TCHCL 10
Address Hold Time to
ALE Inactive
TCLDV
TCHDX
Data Valid Delay
Data Hold Time
10
10
110
10
10
60
ns
ns
ns
ns
ns
ns
ns
b
TCLCH 30
b
TCLCH 30
TWHDX Data Hold Time after WR
TCVCTV Control Active Delay 1
TCHCTV Control Active Delay 2
TCVCTX Control Inactive Delay
10
10
10
0
110
110
110
10
10
10
0
70
60
70
TAZRL
Address Float to READ
Active
TCLRL
TCLRH
TRHAV
RD Active Delay
RD Inactive Delay
10
10
165
150
10
10
100
80
ns
ns
ns
b
TCLCL 45
b
TCLCL 40
RD Inactive to Next
Address Active
TCLHAV HLDA Valid Delay
TRLRH RD Width
TWLWH WR Width
TAVAL Address Valid to ALE Low TCLCH 60
10
160
10
100
ns
ns
ns
ns
ns
ns
b
b
2TCLCL 50
2TCLCL 75
b
b
2TCLCL 40
2TCLCL 60
b
b
TCLCH 40
TOLOH Output Rise Time
TOHOL Output Fall Time
20
12
20
12
From 0.8V to 2.0V
From 2.0V to 0.8V
NOTES:
1. Signal at 8284A shown for reference only. See 8284A data sheet for the most recent specifications.
2. Set up requirement for asynchronous signal only to guarantee recognition at next CLK.
3. Applies only to T2 state (8 ns into T3 state).
18
INTEL [ INTEL ]
