8088
WAVEFORMS (Continued)
BUS TIMINGÐMINIMUM MODE SYSTEM (Continued)
231456–14
NOTES:
1. All signals switch between V
and V unless otherwise specified.
OL
OH
2. RDY is sampled near the end of T , T , T to determine if T machines states are to be inserted.
2
3
w
w
3. Two INTA cycles run back-to-back. The 8088 local ADDR/DATA bus is floating during both INTA cycles. Control
signals are shown for the second INTA cycle.
4. Signals at 8284 are shown for reference only.
5. All timing measurements are made at 1.5V unless otherwise noted.
20
INTEL [ INTEL ]
