8086
Table 1. Pin Description (Continued)
Name and Function
Symbol
S , S , S
(Continued)
Pin No. Type
26–28
O
These signals float to 3-state OFF in ‘‘hold acknowledge’’. These status
lines are encoded as shown.
2
1
0
S
S
S
0
Characteristics
2
1
0 (LOW)
0
0
0
Interrupt Acknowledge
Read I/O Port
Write I/O Port
Halt
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
0
1 (HIGH)
Code Access
Read Memory
Write Memory
Passive
1
1
1
RQ/GT ,
0
RQ/GT
30, 31
I/O
REQUEST/GRANT: pins are used by other local bus masters to force
the processor to release the local bus at the end of the processor’s
current bus cycle. Each pin is bidirectional with RQ/GT having higher
1
0
priority than RQ/GT . RQ/GT pins have internal pull-up resistors and
1
may be left unconnected. The request/grant sequence is as follows
(see Page 2-24):
1. A pulse of 1 CLK wide from another local bus master indicates a local
bus request (‘‘hold’’) to the 8086 (pulse 1).
2. During a T or T clock cycle, a pulse 1 CLK wide from the 8086 to
4
1
the requesting master (pulse 2), indicates that the 8086 has allowed the
local bus to float and that it will enter the ‘‘hold acknowledge’’ state at
the next CLK. The CPU’s bus interface unit is disconnected logically
from the local bus during ‘‘hold acknowledge’’.
3. A pulse 1 CLK wide from the requesting master indicates to the 8086
(pulse 3) that the ‘‘hold’’ request is about to end and that the 8086 can
reclaim the local bus at the next CLK.
Each master-master exchange of the local bus is a sequence of 3
pulses. There must be one dead CLK cycle after each bus exchange.
Pulses are active LOW.
If the request is made while the CPU is performing a memory cycle, it
will release the local bus during T of the cycle when all the following
4
conditions are met:
1. Request occurs on or before T .
2
2. Current cycle is not the low byte of a word (on an odd address).
3. Current cycle is not the first acknowledge of an interrupt acknowledge
sequence.
4. A locked instruction is not currently executing.
If the local bus is idle when the request is made the two possible events
will follow:
1. Local bus will be released during the next clock.
2. A memory cycle will start within 3 clocks. Now the four rules for a
currently active memory cycle apply with condition number 1 already
satisfied.
LOCK
29
O
LOCK: output indicates that other system bus masters are not to gain
control of the system bus while LOCK is active LOW. The LOCK signal
is activated by the ‘‘LOCK’’ prefix instruction and remains active until the
completion of the next instruction. This signal is active LOW, and floats
to 3-state OFF in ‘‘hold acknowledge’’.
4
INTEL [ INTEL ]
