Electrical Specifications
Figure 2-9. Differential Clock Crosspoint Specification
650
600
550
500
550 mV
550 + 0.5 (VHavg - 700)
450
400
250 + 0.5 (VHavg - 700)
350
300
250
200
250 mV
660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850
VHavg (mV)
Figure 2-10. Front Side Bus Common Clock Valid Delay Timing Waveform
T0
T1
T2
BCLK1
BCLK0
TP
Common Clock
Signal (@ driver)
valid
valid
TQ
TR
Common Clock
Signal (@ receiver)
valid
TP = T10: Common Clock Output Valid Delay
TQ = T11: Common Clock Input Setup
TR = T12: Common Clock Input Hold Time
44
64-bit Intel® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet
INTEL [ INTEL ]
