Electrical Specifications
Table 2-23. Miscellaneous Signals AC Specifications (Sheet 2 of 2)
Notes
T# Parameter
Min
Max
Unit
Figure
1,2,5
T38: PROCHOT#, FORCEPR# pulse width
T39: THERMTRIP# assertion until VCC and
500
µs
2-14
2-15
4
6
500
ms
VCACHE removal
T40: FERR# valid delay from STPCLK#
deassertion
0
1
5
BCLKs
ms
2-20
2-18
T41: VCC to PWRGOOD assertion time
500
NOTES:
1. All AC timings for the GTL+ asynchronous signals are referenced to the BCLK0 rising edge at Crossing
Voltage (VCROSS). All GTL+ asynchronous signal timings are referenced at GTLREF. PWRGOOD is
referenced to the BCLK0 rising edge at 0.5 * VTT
.
2. These signals may be driven asynchronously.
3. Refer to the PWRGOOD definition for more details regarding the behavior of the signal.
4. Length of assertion for PROCHOT# does not equal TCC activation time. Time is required after the assertion
or deassertion of PROCHOT# for the processor to enable or disable the TCC. Additionally, time is allocated
after the assertion or deassertion of PROCHOT# for the processor to complete current instruction execution.
This specification applies to the PROCHOT# signal when asserted by the processor and the FORCEPR#
signal when asserted by the system.
5. Refer to Section 8.2 for additional timing requirements for entering and leaving low power states.
6. Intel recommends the VTT power supply also be removed upon assertion of THERMTRIP#.
7. A minimum pulse width of 500us is recommended when FORCEPR# is asserted by the system.
Table 2-24. Front Side Bus AC Specifications (Reset Conditions)
T# Parameter
Min
Max
Unit
Figure
Notes
T47: Reset Configuration Signals (A[21:16]#)
Setup Time
1
ms
1
T45: Reset Configuration Signals (A[39:22]#,
A[15:3]#, BR[3:0]#, INIT#, SMI#) Setup Time
4
2
BCLKs
BCLKs
2-18
2-18
1
2
T46: Reset Configuration Signals (A[39:3]#,
BR[3:0]#, INIT#, SMI#) Hold Time
28
NOTES:
1. Before the clock that de-asserts RESET#
2. After the clock that de-asserts RESET#.
Table 2-25. TAP Signal Group AC Specifications
Notes
T# Parameter
Min
Max
Unit
Figure
1,7
T55: TCK Period
13.3
1.5
3.0
0.5
2
ns
ns
2-7
2
3,6
3,6
4
T61: TDI, TMS Setup Time
T62: TDI, TMS Hold Time
T63: TDO Clock to Output Delay
T64: TRST# Assert Time
2-13
2-13
2-13
2-14
ns
10.0
ns
TCK
5
NOTES:
1. Not 100% tested. These parameters are based on design characterization.
2. This specification is based on the capabilities of the ITP-XDP debug port tool, not on processor silicon.
3. Referenced to the rising edge of TCK.
4. Referenced to the falling edge of TCK.
5. TRST# must be held asserted for 2 TCK periods to be guaranteed that it is recognized by the processor.
40
64-bit Intel® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet
INTEL [ INTEL ]
