Electrical Specifications
Figure 2-11. Source Synchronous 2X (Address) Timing Waveform
T1
T2
TP/4
TP/2
3TP/4
BCLK1
BCLK0
TQ
ADSTB# (@ driver)
A# (@ driver)
TR
TH
TJ
TH
TJ
valid
valid
TK
TS
ADSTB# (@ receiver)
A# (@ receiver)
valid
valid
TM
TN
TP = T1: BCLK[1:0] Period
TH = T23: Source Sync. Address Output Valid Before Address Strobe
TJ = T24: Source Sync. Address Output Valid After Address Strobe
TK = T27: Source Sync. Input Setup Time to BCLK
TM = T25: Source Sync. Input Setup Time
TN = T26: Source Sync. Input Hold Time
TQ = T29: First Address Strobe to Second Address Strobe
TS = T20: Source Sync. Output Valid Delay
TR = T32: Address Strobe Output Valid Delay
64-bit Intel® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet
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INTEL [ INTEL ]
