Electrical Specifications
6. Specification for a minimum swing defined between TAP VT- to VT+. This assumes a minimum edge rate of
0.5 V/ns.
7. It is recommended that TMS be asserted while TRST# is being deasserted.
Table 2-26. VIDPWRGD and Other Voltage Sequence AC Specifications
T# Parameter
T70: VIDPWRGD rise time
Min
Max
Unit
Figure
Notes
150
10
1
ns
ms
ms
ms
ms
2-19
2-19
2-19
2-18
2-18
1
T71: VTT to VIDPWRGD delay time
T72: VTT to VIDPWRGD deassertion time
T73: VIDPWRGD to VCACHE delay time
T74: VCACHE to VCC delay time
1
2
3
0
1
NOTES:
1. Rise time is measured between 10% and 90% points on the waveform.
2. Specification refers to the time between VIDPWRGD = VTT - 20% and VIDPWRGD = VIL.
3. VCACHE to VCC delay time is measured from (0.5 * CVID) to (0.5 * VID).
Table 2-27. VID Signal Group AC Timing Specifications
T# Parameter
T80: VID Step Time
Min
Max
Unit
Figure
Notes
5
µs
µs
µs
µs
µs
µs
2-21, 2-22
2-21, 2-22
2-21
T81: VID Dwell Time
50
T82: VID Down Transition to Valid VCC (min)
T82: VID Up Transition to Valid VCC (min)
T82: VID Down Transition to Valid VCC (max)
T82: VID Up Transition to Valid VCC (max)
0
50
50
0
2-21
2-22
2-22
Table 2-28. SMBus Signal Group AC Specifications
T# Parameter
Min
Max
Unit
Figure
Notes 1,2
T90: SM_CLK Frequency
T91: SM_CLK Period
10
10
100
100
N/A
N/A
1.0
KHz
µs
µs
µs
µs
µs
µs
ns
ns
µs
T92: SM_CLK High Time
T93: SM_CLK Low Time
T94: SMBus Rise Time
T95: SMBus Fall Time
4.0
2-16
2-16
2-16
2-16
2-17
2-16
2-16
2-16
4.7
0.02
0.02
0.1
4
4
0.3
T96: SMBus Output Valid Delay
T97: SMBus Input Setup Time
T98: SMBus Input Hold Time
T99: Bus Free Time
4.5
250
300
4.7
N/A
N/A
N/A
3,5
T100: Hold Time after Repeated Start
Condition
4.0
N/A
µs
2-16
T101: Repeated Start Condition Setup
Time
4.7
4.0
N/A
N/A
µs
µs
2-16
2-16
T102: Stop Condition Setup Time
64-bit Intel® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet
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