®
MOBILE PENTIUM PROCESSOR WITH MMX™ TECHNOLOGY
4.4.2.2.
Settling Time
Use the following procedure to verify board
simulation and tuning with concerns for settling
time.
The settling time is defined as the time a signal
requires at the receiver to settle within 10 percent of
VCC3 or VSS. Settling time is the maximum time
allowed for a signal to reach within 10 percent of its
final value.
·
Simulate settling time at the slow corner for a
particular signal.
·
If settling time violations occur (signal requires
more than 12.5 ns. to settle to + 10 percent of
its final value), simulate signal trace with D.C.
diodes in place at the receiver pin. The D.C.
diode behaves almost identically to the actual
(non-linear) diode on the part as long as
excessive overshoot does not occur.
Most available simulation tools are unable to
simulate settling time so that it accurately reflects
silicon measurements. On
second-order effects and other effects serve to
dampen the signal at the receiver. Because of all
these concerns, settling time is a recommendation
or a tool for layout tuning and not a specification.
a
physical board,
·
·
If settling time violations still occur, simulate
flight times for five consecutive cycles for that
particular signal.
Settling time is simulated at the slow corner, to
make sure that there is no impact on the flight times
of the signals if the waveform has not settled.
Settling time may be simulated with the diodes
included or excluded from the input buffer model. If
diodes are included, settling time recommendation
will be easier to meet.
If flight time values are consistent over the five
simulations, settling time should not be a
concern. If however, flight times are not
consistent over the five simulations, tuning of
the layout is required.
Although simulated settling time has not shown
good correlation with physical, measured settling
time, settling time simulations can still be used as a
tool to tune layouts.
·
Note that, for signals that are allocated two
cycles for flight time, the recommended
settling time is doubled.
Maximum Settling Time to within 10% of V IH or
VIL is: 12.5 nS at 66 MHz
Vih max + 10%
volts
2.5
Vih min - 10%
Figure 13. Settling Time
52
INTEL [ INTEL ]
