Register Description
3.2
Memory-Mapped Registers
• I/OxAPIC. In addition to the PCI Configuration Registers mentioned above, the I/OxAPIC
memory-mapped registers are located in the processor memory space located by the MBAR
Register (PCI offset 10h) and ABAR Register (PCI offset 40h). MBAR and ABAR are located
in the I/OxAPIC PCI Configuration space.
• Standard Hot Plug Controller. In addition to the PCI Configuration Registers mentioned
above, the hot plug controller memory-mapped registers are located in the processor memory
space located by the MBAR Register (PCI offset 10h). MBAR is located in the hot plug
controller PCI Configuration space.
3.3
3.4
SMBus Port Registers
The SMBus does not have any PCI configuration registers. SMBus fields are only accessible via
the SMBus port (see Section 2.17).
Register Nomenclature and Access Attributes
Symbol
Description
RO
Read Only. If a register is read only, writes to this register have no effect.
ROS
Read-Only Sticky. Register bits are read-only and cannot be altered by software. Bits are not
cleared by reset and can only be reset with the PWROK reset condition.
RW
Read/Write. A register with this attribute can be read and written.
RWC
Read/Write Clear. A register bit with this attribute can be read and written. However, a write
of a 1 clears (sets to 0) the corresponding bit and a write of a 0 has no effect.
RWCS
Read and Write One to Clear and Sticky. through reset. Software needs to write a 1 to this
bit to clear it when set. Write of 0 has no effect on this bit. Only a PWROK reset can reset this
bit.
RWO
RWS
Read/Write Once. A register bit with this attribute can be written to only once after power up.
After the first write, the bit becomes read only.
Read-Write and Sticky. Software can read and write from this bit and only a PWROK reset
can reset this bit.
Reserved Bits Some of the Intel® 6702PXH 64-bit PCI Hub registers described in this section contain
reserved bits. These bits are labeled "Reserved”. Software must deal correctly with fields that
are Reserved. On reads, software must use appropriate masks to extract the defined bits and
not rely on reserved bits being any particular value. On writes, software must ensure that the
values of reserved bit positions are preserved. That is, the values of reserved bit positions
must first be read, merged with the new values for other bit positions and then written back.
Note the software does not need to perform read, merge, and write operations for the
configuration address register.
Reserved
Registers
In addition to reserved bits within a register, the Intel® 6702PXH 64-bit PCI Hub contains
address locations in the configuration space that are marked "Reserved”. When a “Reserved”
register location is read, a random value can be returned. (“Reserved” registers can be 8-,
16-, or 32-bit in size). Registers that are marked as “Reserved” must not be modified by
system software. Writes to “Reserved” registers may cause system failure.
78
Intel® 6702PXH 64-bit PCI Hub Datasheet
INTEL [ INTEL ]
