Debug and Logic Analyzer Mode
Table 5-5.
Transfer
N0
N1
N2
N3
N4
N5
N6
N7
N8
N9
N 10
N 11
\
Bit
Typical FBD Southbound Command Frame
9
aE0
aE1
aE2
aE3
FE21
FE20
FE19
FE18
FE17
FE16
FE15
FE14
8
aE7
aE6
aE5
aE4
0
0
0
0
0
0
0
0
7
aE8
aE9
aE10
aE11
0
0
0
0
0
0
0
0
6
F0=0
F1=0
aE13
aE12
0
0
0
0
0
0
0
0
5
aC20
aC21
aC22
aC23
bC20
bC21
bC22
bC23
cC20
cC21
cC22
cC23
4
aC16
aC17
aC18
aC19
bC16
bC17
bC18
bC19
cC16
cC17
cC18
cC19
3
aC12
aC13
aC14
aC15
bC12
bC13
bC14
bC15
cC12
cC13
cC14
cC15
2
aC8
aC9
aC10
aC11
bC8
bC9
bC10
bC11
cC8
cC9
cC10
cC11
1
aC4
aC5
aC6
aC7
bC4
bC5
bC6
bC7
cC4
cC5
cC6
cC7
0
aC0
aC2
aC3
bC0
bC1
bC2
cC0
cC1
cC2
cC3
Output to logic analyzer is lane by lane
early data
[lane 9][lane 1][lane0]
[FE20,FE21,….,aE0] ……… [bC5, bC4, aC7, aC6, aC5, aC4] [bC1, bC0, aC3, aC2, aC1,
aC0]
late data
[lane 9][lane 1][lane0]
[FE14,FE15,….,FE19] … … [cC7, cC6, cC5, cC4, bC7, bC6] [cC3,cC2, cC1, cC0, bC3,
bC2]
Note:
CRC codes in A cmd (aE0 - aE13) are a function of FE21:FE14 of previous frame.
5.1.7
LAI to DDR Pin Timing
The phases of data presented to the logic analyzer have some odd timing due to reuse
of some many different types of DDR I/O outputs to achieve the desired pin count. The
LA will compensate for these predictable phase offsets.
Intel® 6400/6402 Advanced Memory Buffer Datasheet
Late Data
59
bC3
Early Data
aC1
INTEL [ INTEL CORPORATION ]
