Debug and Logic Analyzer Mode
Table 5-3.
LAI Mode Added Signals (Sheet 2 of 2)
Signal Type
CLK
Direction
Out
Definition
Logic analyzer reference clock (differential). This provides a LA
compatible timing reference clock for capture of all signals to the
LA, with fine capture phase adjust using the native LA clock edge
offset capabilities.
Store qualifier:
1 = store
0 = do not store
Drives 1 when LAI pins are valid level. Should be connected to
pull down on LAI board to detect when LAI pins are tri-stated
and LA should ignore data.
Inter-AMB event bus for cross-triggering (wired-OR, high active,
slow).This four bit event bus allows multiple AMB (and similar)
LAIs to be programmed to inter-communicate locally detected
matching and/or filtering opportunities events (cross-triggering
and cross-qualification).
QUAL
Out
FRAME
Out
EV[3:0]
I/O
5.1.5
LAI to DDR Pin Mapping
contains the LAI-to-DDR pin mapping.
Table 5-4.
List of Shared DDR/LAI Pins (Sheet 1 of 2)
DDR Pin
DQ[55:52], DQS[15],
DQS[15]
Count
6
Speed Mbit/sec
533/667
LAI Mode
sbframe_data0[5:0],
[11:6]
Comment
5:0 captured on rising
edge of CLK,
11:6 captured on falling
edge of CLK
DQ[59:56], DQS[7],
DQS[7]
DQ[51:48], DQS[6],
DQS[6]
DQ[39:36], DQS[13],
DQS[13]
DQ[47:44], DQS[14],
DQS[14]
DQ[35:32], DQS[4],
DQS[4]
DQ[43:40], DQS[5],
DQS[5]
RASB, A[10:9)B,
DYBA[2:0]B
A[6:2]B, A[0]B
A[15:11],B A[8]B
CKE[1:0]B, CS[1:0]B,
ODTB,
BA[2]A
CASB, WEB, A[7]B,
A[1]B
CASA
RASA
CKE[1:0]A, CS[1:0]A,
ODTA, WEA
6
6
6
6
6
6
6
6
6
5
1
4
1
1
6
533/667
533/667
533/667
533/667
533/667
533/667
533/667
533/667
533/667
267/333
533/667
100 MHz
267/333
267/333
267/333
sbframe_data1[5:0],
[11:6]
sbframe_data2[5:0],
[11:6]
sbframe_data3[5:0],
[11:6]
sbframe_data4[5:0],
[11:6]
sbframe_data5[5:0],
[11:6]
sbframe_data6[5:0],
[11:6]
sbframe_data7[5:0],
[11:6]
sbframe_data8[5:0],
[11:6]
sbframe_data9[5:0],
[11:6]
trigger[10:6]
frame
evbus[3:0]
mode
qual
trigger[5:0]
Will only change at 1/2
freq
Will only change at 1/2
freq
1 if transferring first half
of frame, 0 if second half
Inner DY bumpout rows
Intel® 6400/6402 Advanced Memory Buffer Datasheet
57
INTEL [ INTEL CORPORATION ]
