Electrical, Power, and Thermal
4.4.11
Advance Memory Buffer Component Electrical Timing
Summary
Table 4-8 and Table 4-9 contain the electrical timing specifications for the Advance
Memory Buffer component DDR2 interface.
Table 4-8.
Advance Memory Buffer Component DDR2 Electrical Timing Specifications
DDR2 667
Min Max
DDR2 533
Unit
s
Symbol
Parameter
Fig #
Min
Max
System Memory Clock Timings
t
Ideal clock (CK) period
CK high time
3.0
3.75
ns
ns
ns
ps
ps
ps
CK
tCH
tCL
tjit
1.35
1.70
1.70
CK low time
1.35
CK cycle to cycle Jitter
CK half-cycle jitter
150
175
4-7
tjit
150
20
175
30
4-7
HP
TDQSCK
Clock rising edge to DQS
rising edge, or clock falling
edge to DQS falling edge --
includes -110/-70 ps for
package
-200
-210
4-10
System Memory Address/Command/Control Signal Timings (Normal)
tCVB
CMD/ADD/CNTL output valid 1260
before CLK/CLK
1615
ps
ps
4-8
4-8
tCVA
CMD/ADD/CNTL output valid 1120
after CLK/CLK -- includes
1475
-140 ps for package
System Memory Address/Command/Control Signal Timings (Early)
tECVB
tECVA
Early CMD/ADD/CNTL output 1760
valid before CLK/CLK
2240
850
4-9
4-9
Early CMD/ADD/CNTL output 620
valid after CLK/CLK --
includes -140 ps for package
System Memory Data and Strobe Signal Timings
tDVB
DQ[63:0], CB[7:0], valid
before DQS[15:0]/
575
575
1.35
750
750
ps
ps
4-6
4-6
DQS[15:0] crossing
tDVA
DQ[63:0], CB[7:0], valid
after DQS[15:0]/DQS[15:0]
crossing
tDOPW
DQ[63:0]. CB[7:0] Output
Valid Pulse Width
1.70
-700
1180
3.58
1.7
ns
ps
ps
ns
ns
tSU
DQ and CB Input Setup Time -530
to DQS Crossing
4-11
4-11
4-12
4-13
AMB
tHD
DQ and CB Input Hold Time
After DQS Crossing
970
AMB
tWPRE
tWPST
DQS Write Preamble
Duration
2.85
1.35
3.5
4.25
2.05
AMB
DQS Write Postamble
Duration
1.65
AMB
50
Intel® 6400/6402 Advanced Memory Buffer Datasheet
INTEL [ INTEL ]
