Electrical, Power, and Thermal
4.4.11
Advance Memory Buffer Component Electrical Timing
Summary
and
contain the electrical timing specifications for the Advance
Memory Buffer component DDR2 interface.
Table 4-8.
Advance Memory Buffer Component DDR2 Electrical Timing Specifications
DDR2 667
Symbol
Parameter
Min
System Memory Clock Timings
t
CK
tCH
tCL
tjit
tjit
HP
TDQSCK
Ideal clock (CK) period
CK high time
CK low time
CK cycle to cycle Jitter
CK half-cycle jitter
Clock rising edge to DQS
rising edge, or clock falling
edge to DQS falling edge --
includes -110/-70 ps for
package
-200
1.35
1.35
150
150
20
-210
3.0
1.70
1.70
175
175
30
3.75
ns
ns
ns
ps
ps
ps
4-7
4-7
4-10
Max
Min
Max
DDR2 533
Unit
s
Fig #
System Memory Address/Command/Control Signal Timings (Normal)
tCVB
CMD/ADD/CNTL output valid
before CLK/CLK
tCVA
CMD/ADD/CNTL output valid
after CLK/CLK -- includes
-140 ps for package
System Memory Address/Command/Control Signal Timings (Early)
tECVB
tECVA
Early CMD/ADD/CNTL output
valid before CLK/CLK
Early CMD/ADD/CNTL output
valid after CLK/CLK --
includes -140 ps for package
1760
620
2240
850
4-9
4-9
1120
1475
ps
4-8
1260
1615
ps
4-8
System Memory Data and Strobe Signal Timings
tDVB
DQ[63:0], CB[7:0], valid
before DQS[15:0]/
DQS[15:0] crossing
DQ[63:0], CB[7:0], valid
after DQS[15:0]/DQS[15:0]
crossing
DQ[63:0]. CB[7:0] Output
Valid Pulse Width
DQ and CB Input Setup Time
to DQS Crossing
DQ and CB Input Hold Time
After DQS Crossing
DQS Write Preamble
Duration
DQS Write Postamble
Duration
575
750
ps
4-6
tDVA
575
750
ps
4-6
tDOPW
tSU
AMB
tHD
AMB
tWPRE
AMB
tWPST
AMB
1.35
-530
970
2.85
1.35
3.5
1.65
1.70
-700
1180
3.58
1.7
4.25
2.05
ns
ps
ps
ns
ns
4-11
4-11
4-12
4-13
50
Intel® 6400/6402 Advanced Memory Buffer Datasheet
INTEL [ INTEL CORPORATION ]
