DDR Interface
3.3.1
CKE Output Control
The are six different functions that affect the state of the CKE outputs during normal
operation:
1. DRC.CKEFRCLOW CSR. When set, this bit forces both CKE outputs low. No other
CKE control function overrides this CSR. This allows firmware to prevent hardware
from issuing all DRAM commands. This could be used by firmware to keep the
DRAM bus idle throughout a fast reset sequence that occurs before the DRAM
initialization command sequence has been initiated.
2. Self-Refresh FSM. When entering a fast reset sequence, a hardware FSM takes
control of the DDR command bus, including the CKE outputs, in order to issue a
series of commands to put the DRAM’s into self-refresh. This FSM is overridden by
the DRC.CKEFRCLOW CSR.
3. Automatic self-refresh exit with link training. When a T0 link training sequence is
complete, both CKE outputs will be automatically asserted high in order to exit self-
refresh. This control is inhibited by setting the DSREFTC.DISSREXIT bit. The
DRC.CKEFRCLOW also overrides this automatic self-refresh exit function.
4. Self-Refresh entry DCALCSR command. The DCALCSR register can be programmed
to launch an FSM that issues a single self-refresh entry command. The
DRC.CKEFRCLOW bit overrides this function.
5. Channel commands. The host can directly control the CKE output state through
channel command protocol. The DRC.CKEFRCLOW bit overrides this function.
6. DRC CKE0 and CKE1 CSR bits. These CKE bits in the DRC are both control and
status bits for the CKE outputs. Software can write these bits to directly control the
CKE outputs. These bits reflect the state of the CKE outputs one cycle after the
output state is changed by one of the other control functions. The
DRC.CKEFRCLOW bit overrides this function.
Channel commands that change the state of the same CKE output must be separated
by at least two DRAM clock cycles. Configuration writes and channel commands that
affect the same CKE output must not occur within two cycles of each other to avoid
unstable CKE behavior.
3.4
DQS I/O and DM Outputs
The AMB sends and receives source synchronous differential strobes (DQS) to transfer
data (DQ/CB) during write and read DRAM transactions. DQS9 through DQS17 also
support the data mask (DM) function in x8 mode. Setting the MTR.WIDTH configuration
register enables x8 mode. When driving DM, the timing of the transition from floating,
to driving, and back to floating is unchanged, but DQS[17:9] do not toggle and instead
drive a constant level. DQSP[17:9] drive low and DQSN[17:9] drive high. In x8 mode
DQS[17:9] are not used to capture read data. The table below lists which DQS signals
are associated with which DQ/CB pins in x8 and x4 mode.
Table 3-1.
DQS Association with DQ/CB Pins in x8 and x4 Mode
x4 Mode: MTR.WIDTH=0
x8 Mode: MTR.WIDTH=1
DQS Pin
Output
Function
Input/Output
Data Mapping
Output
Function
Input/Output
Data Mapping
DQS17
Write DQS
CB[7:4]
DM
N/A
DQS8
Write DQS
Write DQS
CB[3:0]
Write DQS
DM
CB[7:0]
N/A
DQS16
DQ[63:60]
Intel® 6400/6402 Advanced Memory Buffer Datasheet
27
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