FBD Channel Interface
DRAM SCLK is placed at the center of the command window which adds an additional
6UI of delay. The DRAMs are programmed with a TRead_Latency of 4. The DQS strobes
are centered when they get to the AMB (3UI delay) and the data takes an additional 10
UI to propagate from the DDR I/O to the NB FBD I/O (including setup time at NB FBD
and CRC generation) before it can be clocked into the NB FBD for transmission. The
total delay without including the DRAM access time in this case is (10 + 6 + 3 + 10UI)
29UI. The CMD2DATANXT.DLYFRMS will be programmed with a value 2 and the
CMD2DATANXT.DLYFRAC with 5UI. If the AMB supports only a 2UI granularity, then the
values should be 2 frames and 6UI respectively. If an AMB does not support sub-frame
delays, it is expected that the value in SPD will be round up the to the nearest frame.
Any additional delays caused by rounding up should be supported by additional
buffering in the DDR I/O.
The above figure shows the last arriving data from the DDR. It is expected that any
data arriving earlier than this, due to differences in routing, and so forth, is buffered up
in some way inside the DDR I/O. The expectation is that all AMBs (last and
intermediate) unload the data from the DDR I/O with the timing specified by the
TCMD_To_DATA. The Last AMB is expected to be able send data on the NB links with no
additional delay added, if C2DINCRCUR.INCRDLY is 0. Any additional delay needed due
to the value programmed in C2DINCRCUR.INCRDLY register in the last AMB or to delay
the data in intermediate AMB before the merge, is handled by FIFOs in the AMB core.
In the above figure, it is assumed that the AMB can place the clocks in position shown
above. If this is not the case, then additional delays due to non-optimal placement of
the clocks should be taken into account to calculate the total delay to be programmed
into the SPD.
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Intel® 6400/6402 Advanced Memory Buffer Datasheet
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