DDR Interface
Table 3-1.
DQS Association with DQ/CB Pins in x8 and x4 Mode
x4 Mode: MTR.WIDTH=0
x8 Mode: MTR.WIDTH=1
DQS Pin
Output
Function
Input/Output
Data Mapping
Output
Function
Input/Output
Data Mapping
DQS7
Write DQS
DQ[59:56]
DQ[55:52]
DQ[51:48]
DQ[47:44]
DQ[43:40]
DQ[39:36]
DQ[35:32]
DQ[31:28]
DQ[27:24]
DQ[23:20]
DQ[19:16]
DQ[15:12]
DQ[11:8]
DQ[7:4]
Write DQS
DQ[63:56]
N/A
DQS15
DQS6
DQS14
DQS5
DQS13
DQS4
DQS12
DQS3
DQS11
DQS2
DQS10
DQS1
DQS9
DQS0
Write DQS
Write DQS
Write DQS
Write DQS
Write DQS
Write DQS
Write DQS
Write DQS
Write DQS
Write DQS
Write DQS
Write DQS
Write DQS
Write DQS
DM
Write DQS
DM
DQ[55:48]
N/A
Write DQS
DM
DQ[47:40]
N/A
Write DQS
DM
DQ[39:32]
N/A
Write DQS
DM
DQ[31:24]
N/A
Write DQS
DM
DQ[23:16]
N/A
Write DQS
DM
DQ[15:8]
N/A
DQ[3:0]
Write DQS
DQ[7:0]
3.5
Refresh
The AMB is required to manage DRAM refresh during channel resets and when the
auto-refresh function is enabled. During channel resets, the Self-Refresh FSM takes
control of the DDR command bus and places the DRAMs in self-refresh mode. The
Auto-Refresh FSM generates auto-refresh commands when the DAREFTC.AREFEN bit is
set. The Self-Refresh FSM will override and take control away from the Auto-Refresh
FSM when a reset event occurs.
A self-refresh entry command can also be generated by programming the DCALCSR
register. The FSM that controls this function will be described in the DRAM initialization
and (E)MRS command section.
28
Intel® 6400/6402 Advanced Memory Buffer Datasheet
INTEL [ INTEL ]
