DDR Interface
3 DDR Interface
3.1
Intel 6400/6402 Advanced Memory Buffer (AMB)
DDR Interface Overview
The DDR interface on the AMB consists of:
• A command decoder.
• A FIFO write buffer to hold the write data before it is written to the DDR channel.
The write FIFO buffer has 36 entries of 72 bits (36 x 72b). A maximum of 35
entries can be used to store DDR bursts. Write data targeted for other AMB parts
on the channel will use three of the 35 entries until the target AMB is known. The
write FIFO buffer fills at half of the DDR data rate, and empties at the DDR data
rate. The write FIFO buffer must support an invalidate write FIFO command (FBD
Soft Reset command).
• A FIFO read buffer to hold the read data so that each DIMM returns data with the
same latency as the southernmost DIMM in the chain. Latency is measured in
increments of core clock periods. The core clock runs at the DDR command clock
rate (half the data rate frequency). The latency through the FIFO read buffer on the
southernmost DIMM is expected to be zero.
• A DDR cluster which serves as a DIMM buffer by registering outbound commands
and data at output flops. The cluster also captures and levelizes incoming read
data.
• A reset FSM which puts the DIMM in self-refresh when reset is asserted, and exits
self-refresh when reset is deasserted and southbound frame training is complete.
• A calibration FSM that automatically sets the timing for DQS receiver enable and
DQS delay or equivalent DDR timing control mechanism. The DQS receiver enable
calibration uses a series of DRAM read and write operations to find the center of the
read DQS preamble. During normal operation the DQS receivers will be enabled at
the preamble center to ensure that the DQS signal is received correctly into the
AMB Component’s DDR I/O circuits. The DQS delay calibration uses a series of
reads and writes to align the read DQS waveform rising and falling edges to the
center of the DQ data eye.
• A configuration register set to allow software to issue DRAM power up and DRAM
MRS/EMRS commands, as well as a self-refresh entry command. These registers
are accessible through FBD channel commands and the SMBUS interface.
• “Burst Write Interrupt” is not supported.
3.2
Data Mapping
See the protocol chapter of the FB DIMM Architecture and Protocol Specification for the
mapping between data in DDR DRAM devices and data in FBD frame formats for 4-bit
and 8-bit devices.
Intel® 6400/6402 Advanced Memory Buffer Datasheet
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