DDR MemBIST
11.4.5
Test a Range of DRAM Addresses With March C- Algorithm
The following points describe the programming required to test all of the addresses
within a selected address range using the March C- algorithm provided by MemBIST.
1. Set up registers for normal DRAM operation.
2. Program MB_START_ADDR and MB_END_ADDR registers to the desired address
range to be tested. If the full address of the DIMM is to be tested, it must be
programmed here.
3. No user data is required, as all built-in testing algorithms use the fixed data pattern
0xA (regardless of the pattern selected by MBCSR:fixed). Therefore, the
MBDATA[9:0] and MBLFSRSED registers are not written.
4. Program MBCSR.
These fields are required for the specified test:
— Set ALGO (bits 26:24) to 110 to select the built-in March C- testing algorithm.
— Program CMD (bits [5:4]) to be 01 (write only without data comparison), as
this is required for the March C- algorithm.
The values for these fields can be selected to choose options for use during
MemBIST operation:
— Select either Rank 0 or Rank 1 by programming CS (bits [21:20]).
— Program FAST (bits [11:10]) to select Fast X, Fast Y, Fast XY, or XZY
(column->bank->row) address sequencing.
These bits are taken over by the algorithm engine to execute the algorithm. Set
them to their default values.
— FIXED (bits [18:16]).
— ADIR (bit 12).
— ABAR (bit 13).
— DTYPE (bits [9:8]).
— ATYPE (bits [7:6]).
— ENABLE288 (bit 15)
— INVERT (bit 19).
— MBDATA (bit 14). This bit is irrelevant because algorithms always use fixed
data, so both failure data bit lane accumulator and failure addresses are logged
in MBDATA.
Set these control values to start the MemBIST engine.
— Set ABORT (bit 28) to 0.
— Clear PF (bit 30). Hardware will set this bit if a failure is detected.
— If desired to halt whenever there is an error, set HALT (bit 29).
— Set START (bit 31) to 1 to start MemBIST execution.
5. Check the MemBIST results, and if checking was enabled, observe failure data or
address through MBDATA registers and MB_ERR_DATA registers:
— Check MBCSR:start. 0 means MemBIST has completed. Check MBCSR:PF. 1
means a failure has occurred.
— Failure data bit location accumulator will be stored in MBDATA[8, 3:0]. Up to 5
failure addresses will be placed in MBDATA[9, 7:4]. Use the “Fixed Data
Pattern” mapping for these registers.
— Failure data will be stored in MB_ERR_DATA[3:0][4:0] registers.
Intel® 6400/6402 Advanced Memory Buffer Datasheet
137
INTEL [ INTEL ]
