DDR MemBIST
3. Random data is created by the LFSR using the seed value in MBLFSRSED. Either a
value can be written, or the default value can be used. MBDATA[9:0] is unused and
is therefore not written.
4. Program MBCSR.
These fields are required for the specified test:
— Program DTYPE (bits [9:8]) to 11 to select LFSR-generated random data.
— Program CMD (bits [5:4]) to be 11 (write followed by read with data
comparison).
— Program ATYPE (bits [7:6]) to 10 to use the address range already defined in
the MB_START_ADDR and MB_END_ADDR registers.
— Select either Rank 0 or Rank 1 by programming CS (bits [21:20]).
— ENABLE288 (bit 15) is not relevant when random LFSR data has been selected.
INVERT (bit 19) is unnecessary for random data. Rewrite these fields with their
default values.
The values for these fields can be selected to choose options for use during
MemBIST operation:
— Program ABAR (bit 13) to select DAI if desired.
— Program FAST (bits [11:10]) to select Fast X, Fast Y, Fast XY, or XZY (column-
>bank->row) address sequencing.
— Program ADIR (bit 12) to select whether addresses should increment or
decrement.
— MBDATA (bit 14) is set to select failure address logging or failure data bit
location accumulator logging in MBDATA.
Set these control values to start the MemBIST engine.
— Set ALGO (bits 26:24) to 0 to prevent the algorithm engine from overwriting
bits it controls in MBCSR.
— Set ABORT (bit 28) to 0.
— Clear PF (bit 30). Hardware will set this bit if a failure is detected.
— If desired to halt whenever there is an error, set HALT (bit 29).
— Set START (bit 31) to 1 to start MemBIST execution.
5. Check the MemBIST results, and if a failure occurred, observe failure data or
address through MBDATA registers and MB_ERR_DATA registers:
— Check MBCSR:start. 0 means MemBIST has completed. Check MBCSR:PF. 1
means a failure has occurred.
— Depending upon the value chosen for MBCSR:mbdata, either up to 5 failure
addresses or the failure data bit location accumulator will be stored in
MBDATA[8, 3:0].
— Failure data will be stored in MB_ERR_DATA[3:0][4:0] registers.
11.4.3
Write Leaping 0s to the Full DRAM Address Range and
Check
This describes writing leaping 0s to all locations in the DRAM on the DIMM and checking
this data. Leaping 0s are like walking 0s except that rather than moving from bit to
adjacent bit, the single 0 in a field of 1s moves from one bit to another bit far removed
from it. Of every 160 writes to the DRAMs, 144 will have a 0 on some bit, and 16 will
have no 0s on any bit. Refer to the tables and block diagram above to see how this
works.
1. Set up registers for normal DRAM operation.
134
Intel® 6400/6402 Advanced Memory Buffer Datasheet
INTEL [ INTEL ]
