DDR MemBIST
11.5.2
MB Flow Control State Machine
Figure 11-7. MBFSM Diagram
core_rst_l =0
M em Bist M BFSM
IDLE
m bstart &
(wronly |
wrrdcm p)
Always
RD_DONE
W R_START
lfsrdata
rdidle & ~rd2wr
or
wridle & rd2wr
W R_SEED
~ lfsrdata
RD_W AIT
cget &
lastaddr &
rd2wr
RD_W RAVL
ta r t &
m b s rd c m p )
|
o n ly
(rd
cget & lastaddr & ~rdw2wr
lfsrseed_done
W R_NXTAD
Always
wronly
RD_AVAIL
cget & ~lastaddr
Always
cget & rd2wr
RD_NXTW R
W R_AVAIL
cget &
~lastaddr &
~rd2wr
Always
cget &
~lastaddr &
rd2wr
RD_NXTAD
cget & lastaddr
lfsrseed_done
W R_W AIT
~ lfsrdata
RD_SEED
writeidle
lfsrdata
W R_DO NE
~wronly
RD_START
This FSM controls the MemBIST flow and generates read/write commands for
MemBIST.
• When MBCSR bit[31] is programmed to begin execution, the MemBIST FSM will
transition out of the IDLE state to either WR_START or RD_START, depending upon
the MemBIST command programmed in MBCSR:cmd.
• In WR_START state, FSM will look at the decoding of DATA type selection. If LFSR
data type generation is selected, FSM will go to WR_SEED state. If not, FSM will
directly go to WR_NXTAD state.
Intel® 6400/6402 Advanced Memory Buffer Datasheet
139
INTEL [ INTEL CORPORATION ]
