Electrical Specifications
2.6.1
FSB Signal Groups
The front side bus signals have been combined into groups by buffer type. GTL+ input
signals have differential input buffers that use GTLREF[1:0] as a reference level. In this
document, the term “GTL+ Input” refers to the GTL+ input group as well as the GTL+
I/O group when receiving. Similarly, “GTL+ Output” refers to the GTL+ output group as
well as the GTL+ I/O group when driving.
With the implementation of a source synchronous data bus comes the need to specify
two sets of timing parameters. One set is for common clock signals that are dependent
on the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the
source synchronous signals that are relative to their respective strobe lines (data and
address) as well as the rising edge of BCLK0. Asychronous signals are still present
(A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle.
Table 7 identifies which signals are common clock, source synchronous, and
asynchronous.
Table 7.
FSB Signal Groups (Sheet 1 of 2)
Signal Group
Type
Signals1
GTL+ Common
Clock Input
Synchronous to
BCLK[1:0]
BPRI#, DEFER#, RESET#, RS[2:0]#, RSP#, TRDY#
AP[1:0]#, ADS#, BINIT#, BNR#, BPM[5:0]#, BR0#,
DBSY#, DP[3:0]#, DRDY#, HIT#, HITM#, LOCK#,
MCERR#
GTL+ Common
Clock I/O
Synchronous to
BCLK[1:0]
Signals
Associated Strobe
REQ[4:0]#, A[16:3]#3
A[35:17]#3
ADSTB0#
ADSTB1#
GTL+ Source
Synchronous I/O
Synchronous to
assoc. strobe
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
DSTBP0#, DSTBN0#
DSTBP1#, DSTBN1#
DSTBP2#, DSTBN2#
DSTBP3#, DSTBN3#
Synchronous to
BCLK[1:0]
GTL+ Strobes
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
GTL+
Asynchronous
Input
A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#,
STPCLK#, PWRGOOD
GTL+
Asynchronous
Output
FERR#/PBE#, IERR#, THERMTRIP#
GTL+
Asynchronous
Input/Output
PROCHOT#
Synchronous to
TCK
TAP Input
TCK, TDI, TMS, TRST#
Datasheet
23
INTEL [ INTEL ]
