Electrical Specifications
Table 7.
FSB Signal Groups (Sheet 2 of 2)
Signal Group
Type
Signals1
Synchronous to
TCK
TAP Output
FSB Clock
TDO
BCLK[1:0], ITP_CLK[1:0]2
Clock
VCC, VTT, VCCA, VCCIOPLL, VID[5:0], VSS, VSSA,
GTLREF[1:0], COMP[5:4,1:0], RESERVED, TESTHI[13:0],
THERMDA, THERMDC, VCC_SENSE,
VCC_MB_REGULATION, VSS_SENSE,
Power/Other
VSS_MB_REGULATION, BSEL[2:0], SKTOCC#, DBR#2,
VTTPWRGD, BOOTSELECT, VTT_OUT_LEFT,
VTT_OUT_RIGHT, VTT_SEL, LL_ID[1:0], MSID[1:0], FCx,
IMPSEL
NOTES:
1.
2.
Refer to Section 4.2 for signal descriptions.
In processor systems where no debug port is implemented on the system board, these
signals are used to support a debug port interposer. In systems with the debug port
implemented on the system board, these signals are no connects.
The value of these signals during the active-to-inactive edge of RESET# defines the
processor configuration options. See Section 6.1 for details.
3.
.
Table 8.
Signal Characteristics
Signals with RTT
Signals with No RTT
A20M#, BCLK[1:0], BPM[5:0]#, BSEL[2:0],
COMP[5:4,1:0], FERR#/PBE#, IERR#,
IGNNE#, INIT#, ITP_CLK[1:0], LINT0/INTR,
LINT1/NMI, PWRGOOD, RESET#, SKTOCC#,
SMI#, STPCLK#, TDO, TESTHI[13:0],
THERMDA, THERMDC, THERMTRIP#,
VID[5:0], VTTPWRGD, GTLREF[1:0], TCK,
TDI, TMS, TRST#, VTT_SEL
A[35:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#,
BINIT#, BNR#, BOOTSELECT1, BPRI#,
D[63:0]#, DBI[3:0]#, DBSY#, DEFER#,
DP[3:0]#, DRDY#, DSTBN[3:0]#,
DSTBP[3:0]#, HIT#, HITM#, LOCK#, MCERR#,
MSID[1:0]1, PROCHOT#, REQ[4:0]#, RS[2:0]#,
RSP#, TRDY#, IMPSEL1
Open Drain Signals2
THERMTRIP#, FERR#/PBE#, IERR#, BPM[5:0]#,
BR0#, TDO, LL_ID[1:0], FCx
NOTES:
1. These signals have a 500–5000 Ω pull-up to V rather than on-die termination.
TT
2. Signals that do not have R , nor are actively driven to their high-voltage level.
TT
Table 9.
Signal Reference Voltages
GTLREF
VTT/2
BPM[5:0]#, LINT0/INTR, LINT1/NMI, RESET#,
BINIT#, BNR#, HIT#, HITM#, MCERR#, PROCHOT#, BOOTSELECT, VTTPWRGD, A20M#,
BR0#, A[35:0]#, ADS#, ADSTB[1:0]#, AP[1:0]#,
BPRI#, D[63:0]#, DBI[3:0]#, DBSY#, DEFER#,
DP[3:0]#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#,
LOCK#, REQ[4:0]#, RS[2:0]#, RSP#, TRDY#
IGNNE#, INIT#, MSID[1:0],
PWRGOOD1, SMI#, STPCLK#, TCK1,
TDI1, TMS1, TRST#1
NOTES:
1. These signals also have hysteresis added to the reference voltage. See Table 12 for more
information.
24
Datasheet
INTEL [ INTEL ]
