Switching Characteristics
Page 31
Table 28. Transceiver Specifications for Stratix V GT Devices (Part 2 of 5) (1)
Transceiver
Transceiver
Symbol/
Speed Grade 2
Speed Grade 3
Conditions
Unit
Description
Min
—
—
—
—
—
Typ
Max
-70
-90
Min
—
—
—
—
—
Typ
Max
-70
-90
100 Hz
1 kHz
—
—
—
—
—
—
—
—
—
—
Transmitter REFCLK
Phase Noise (622
MHz) (18)
10 kHz
100 kHz
≥ 1 MHz
-100
-110
-120
-100
-110
-120
dBc/Hz
Transmitter REFCLK
Phase Jitter (100
MHz) (15)
10 kHz to
1.5 MHz
(PCIe)
—
—
—
3
—
—
—
3
ps (rms)
1800
1%
1800
1%
RREF (17)
—
—
—
Transceiver Clocks
PCIe
Receiver
Detect
fixedclkclock
frequency
100 or
125
100 or
125
—
—
—
—
MHz
MHz
Reconfiguration clock
(mgmt_clk_clk
)
—
100
—
125
100
—
125
frequency
Receiver
Supported I/O
Standards
—
1.4-V PCML, 1.5-V PCML, 2.5-V PCML, LVPECL, and LVDS
Data rate
GX channels
600
—
8500
600
—
8500
Mbps
(Standard PCS) (21)
Data rate
GX channels
GT channels
GT channels
600
19,600
—
—
—
—
12,500
28,050
1.2
600
19,600
—
—
—
—
12,500
25,780
1.2
Mbps
Mbps
V
(10G PCS) (21)
Data rate
Absolute VMAX for a
receiver pin
(3)
Absolute VMIN for a
receiver pin
GT channels
–0.4
—
—
—
—
–0.4
—
—
—
—
V
V
Maximum peak-to-peak GT channels
differential input
1.6
1.6
voltage VID (diff p-p)
(8)
GX channels
before device
configuration (20)
GT channels
Maximum peak-to-peak
differential input
voltage VID (diff p-p)
VCCR_GTB
1.05 V
=
—
—
—
2.2
—
—
—
—
2.2
—
V
(VICM
=
after device
0.65 V)
(20)
configuration (16)
,
(8)
GX channels
GT channels
Minimum differential
200
200
mV
eye opening at receiver
(8)
GX channels
(4) (20)
serial input pins
,
December 2015 Altera Corporation
Stratix V Device Datasheet
INTEL [ INTEL ]
