Switching Characteristics
Page 33
Table 28. Transceiver Specifications for Stratix V GT Devices (Part 4 of 5) (1)
Transceiver
Transceiver
Symbol/
Speed Grade 2
Speed Grade 3
Conditions
Unit
Description
Min
19,600
—
Typ
—
Max
28,050
—
Min
Typ
—
Max
25,780
—
Data rate
GT channels
GT channels
GX channels
GT channels
GX channels
GT channels
GX channels
19,600
Mbps
100
—
(8)
100
Differential on-chip
termination resistors
—
—
500
15
—
—
—
(8)
500
15
—
—
mV
ps
VOCM (AC coupled)
Rise/Fall time
—
(8)
Intra-differential pair
skew
(8)
(8)
GX channels
Intra-transceiver block
transmitter channel-
to-channel skew
GX channels
Inter-transceiver block
transmitter channel-
to-channel skew
(8)
GX channels
CMU PLL
Supported Data Range
—
—
—
600
1
—
—
—
12500
—
600
1
—
—
—
8500
—
Mbps
µs
(13)
tpll_powerdown
(14)
tpll_lock
—
10
—
10
µs
ATX PLL
VCO post-
divider L=2
8000
—
12500
8000
—
8500
Mbps
L=4
L=8
4000
2000
—
—
6600
3300
4000
2000
—
—
6600
3300
Mbps
Mbps
Supported Data Rate
Range for GX Channels
L=8,
Local/Central
Clock Divider
=2
1000
9800
—
1762.5
1000
9800
—
1762.5
Mbps
Supported Data Rate
Range for GT Channels
VCO post-
divider L=2
—
14025
—
12890
Mbps
(13)
tpll_powerdown
—
—
1
—
—
—
10
1
—
—
—
10
µs
µs
(14)
tpll_lock
—
—
fPLL
3250/
3250/
Supported Data Range
—
—
600
1
—
—
600
1
—
Mbps
µs
3.125 (23)
3.125 (23)
—
(13)
tpll_powerdown
—
—
December 2015 Altera Corporation
Stratix V Device Datasheet
INTEL [ INTEL ]
