7–16
Chapter 7: User Flash Memory in MAX V Devices
Software Support for UFM Block
Figure 7–11. Slave Address Bits
MSB
1
LSB
1- or 2-Kbit Memory Size
0
0
0
1
1
1
0
0
0
A
A
A
A
A
A R/W
0
2
2
2
1
1
MSB
1
LSB
4-Kbit Memory Size (1)
8-Kbit Memory Size (2)
a8 R/W
MSB
1
LSB
a9 a8 R/W
Notes to Figure 7–11:
(1) For the 4-Kbit memory size, the A0 location in the slave address becomes the MSB (a8) of the memory byte
address.
(2) For the 8-Kbit memory size, the A0 location in the slave address becomes a8 of the memory byte address, while
the A1 location in the slave address becomes the MSB (a9) of the memory byte address.
After the master sends a start condition and the slave address byte, the ALTUFM_I2C
logic monitors the bus and responds with an acknowledge (on the SDA line) when its
address matches the transmitted slave address. The ALTUFM_I2C megafunction then
performs a read or write operation to or from the UFM, depending on the state of the
bit.
Byte Write Operation
The master initiates a transfer by generating a start condition, then sending the correct
slave address (with the R/W bit set to 0) to the slave. If the slave address matches, the
ALTUFM_I2C slave acknowledges on the ninth clock pulse. The master then transfers
an 8-bit byte address to the UFM, which acknowledges the reception of the address.
The master transfers the 8-bit data to be written to the UFM. After the ALTUFM_I2C
logic acknowledges the reception of the 8-bit data, the master generates a stop
condition. The internal write from the MAX V logic array to the UFM begins only
after the master generates a stop condition. While the UFM internal write cycle is in
progress, the ALTUFM_I2C logic ignores any attempt made by the master to initiate a
new transfer. Figure 7–12 shows the byte write sequence.
Figure 7–12. Byte Write Sequence
S
Slave Address
A
Byte Address
A
Data
A
P
R/W
"0" (write)
From Master to Slave
From Slave to Master
S – Start Condition
P – Stop Condition
A – Acknowledge
MAX V Device Handbook
January 2011 Altera Corporation