Chapter 1: MAX V Device Family Overview
Integrated Software Platform
1–3
the necessary power pins for migration. For I/O pin migration across densities, cross
reference the available I/O pins using the device pin-outs for all planned densities of
a given package type to identify which I/O pins can be migrated. The Quartus
®
II
software can automatically cross-reference and place all pins for you when given a
device migration list.
Table 1–2. MAX V Packages and User I/O Pins
Device
5M40Z
5M80Z
5M160Z
5M240Z
5M570Z
5M1270Z
5M2210Z
Note to
(1) Device packages under the same arrow sign have vertical migration capability.
64-Pin
MBGA
30
30
—
—
—
—
—
64-Pin
EQFP
54
54
54
—
—
—
—
68-Pin
MBGA
—
52
52
52
—
—
—
100-Pin
TQFP
—
79
79
79
74
—
—
100-Pin
MBGA
—
—
79
79
74
—
—
144-Pin
TQFP
—
—
—
114
114
114
—
256-Pin
FBGA
—
—
—
—
159
211
203
324-Pin
FBGA
—
—
—
—
—
271
271
Table 1–3. MAX V Package Sizes
Package
Pitch (mm)
Area (mm
2
)
Length × width
(mm × mm)
64-Pin
MBGA
0.5
20.25
4.5 × 4.5
64-Pin
EQFP
0.4
81
9×9
68-Pin
MBGA
0.5
25
5×5
100-Pin
TQFP
0.5
256
16 × 16
100-Pin
MBGA
0.5
36
6×6
144-Pin
TQFP
0.5
484
22 × 22
256-Pin
FBGA
1
289
17 × 17
324-Pin
FBGA
1
361
19 × 19
Integrated Software Platform
The Quartus II software provides an integrated environment for HDL and schematic
design entry, compilation and logic synthesis, full simulation and advanced timing
analysis, and programming of MAX V devices.
f
For more information about the Quartus II software features, refer to the
You can debug your MAX V designs using In-System Sources and Probes Editor in
the Quartus II software. This feature allows you to easily control any internal signal
and provides you with a completely dynamic debugging environment.
f
For more information about the In-System Sources and Probes Editor, refer to the
chapter of the
Quartus II
Handbook.
Device Pin-Outs
f
For more information, refer to the
page.
Altera Corporation
INTEL [ INTEL CORPORATION ]
