2–2
Chapter 2: MAX V Architecture
Functional Description
Figure 2–1
shows a functional block diagram of the MAX V device.
Figure 2–1. Device Block Diagram
IOE
IOE
IOE
IOE
IOE
IOE
IOE
Logic
Element
Logic
Element
Logic
Element
IOE
Logic
Element
Logic
Element
Logic
Element
Logic Array
BLock (LAB)
MultiTrack
Interconnect
IOE
Logic
Element
Logic
Element
Logic
Element
IOE
Logic
Element
Logic
Element
Logic
Element
MultiTrack
Interconnect
Each MAX V device contains a flash memory block within its floorplan. This block is
located on the left side of the 5M40Z, 5M80Z, 5M160Z, and 5M240Z devices. On the
5M240Z (T144 package), 5M570Z, 5M1270Z, and 5M2210Z devices, the flash memory
block is located on the bottom-left area of the device. The majority of this flash
memory storage is partitioned as the dedicated configuration flash memory (CFM)
block. The CFM block provides the non-volatile storage for all of the SRAM
configuration information. The CFM automatically downloads and configures the
logic and I/O at power-up, providing instant-on operation.
f
For more information about configuration upon power-up, refer to the
chapter.
A portion of the flash memory within the MAX V device is partitioned into a small
block for user data. This user flash memory (UFM) block provides 8,192 bits of
general-purpose user storage. The UFM provides programmable port connections to
the logic array for reading and writing. There are three LAB rows adjacent to this
block, with column numbers varying by device.
December 2010
Altera Corporation
INTEL [ INTEL CORPORATION ]
