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5M160ZE64C4N 参数 Datasheet PDF下载

5M160ZE64C4N图片预览
型号: 5M160ZE64C4N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 7.9ns, 128-Cell, CMOS, PQFP64, 9 X 9 MM, 0.40 MM PITCH, LEAD FREE, PLASTIC, EQFP-64]
分类和应用: 时钟可编程逻辑
文件页数/大小: 166 页 / 3966 K
品牌: INTEL [ INTEL ]
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5–4  
Chapter 5: Using MAX V Devices in Multi-Voltage Systems  
5.0-V Device Compatibility  
Figure 5–3 shows MAX V device compatibility with 5.0-V CMOS devices.  
Figure 5–3. MAX V Device Compatibility with 5.0-V CMOS Devices  
5.0 V 0.5 V  
3.3 V  
V
V
CCIO  
CCIO  
V
CCIO  
(1)  
REXT  
Open Drain  
VOUT  
Model as RINT  
5.0-V CMOS  
Device  
A
VIN  
VSS  
Note to Figure 5–3:  
(1) This diode is only active after power-up. MAX V devices require an external diode if driven by 5.0 V before  
power-up.  
The open-drain pin never drives high, only low or tri-state. When the open-drain pin  
is active, it drives low. When the open-drain pin is inactive, the pin is tri-stated and  
the trace pulls up to 5.0 V by the external resistor. The purpose of enabling the I/O  
clamp diode is to protect the MAX V device’s I/O pins. The 3.3-V VCCIO supplied to  
the I/O clamp diodes causes the voltage at point A to clamp at 4.0 V, which meets the  
MAX V device’s reliability limits when the trace voltage exceeds 4.0 V. The device  
operates successfully because a 5.0-V input is within its input specification.  
1
The I/O clamp diode is only supported in the 5M1270Z and 5M2210Z devices’ I/O  
Bank 3. You must have an external protection diode for the other I/O banks in the  
5M1270Z and 5M2210Z devices and all the I/O pins in the 5M40Z, 5M80Z, 5M160Z,  
5M240Z, and 5M570Z devices.  
The pull-up resistor value must be small enough for a sufficient signal rise time, but  
large enough so that it does not violate the IOL (output low) specification of the  
MAX V devices.  
The maximum MAX V device IOL depends on the programmable drive strength of the  
I/O output. Table 5–1 lists the programmable drive strength settings that are available  
for the 3.3-V LVTTL/LVCMOS I/O standard for MAX V devices. The Quartus II  
software uses the maximum current strength as the default setting. The PCI I/O  
standard is always set to 20 mA with no alternate setting.  
Table 5–1. 3.3-V LVTTL/LVCMOS Programmable Drive Strength (Part 1 of 2)  
I/O Standard  
IOH/IOL Current Strength Setting (mA)  
16  
8
3.3-V LVTTL  
MAX V Device Handbook  
December 2010 Altera Corporation  
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