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5M160ZE64C4N 参数 Datasheet PDF下载

5M160ZE64C4N图片预览
型号: 5M160ZE64C4N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 7.9ns, 128-Cell, CMOS, PQFP64, 9 X 9 MM, 0.40 MM PITCH, LEAD FREE, PLASTIC, EQFP-64]
分类和应用: 时钟可编程逻辑
文件页数/大小: 166 页 / 3966 K
品牌: INTEL [ INTEL ]
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Chapter 5: Using MAX V Devices in Multi-Voltage Systems  
5–7  
Recommended Operating Conditions for 5.0-V Compatibility  
As shown in Figure 5–5, R1 = 5.0 V/135 mA.  
The values usually shown in the data sheets reflect typical operating conditions.  
Subtract 20% from the data sheet value for guard band. When you subtract the 20%  
from the previous example, the R1 value is 30.  
Select R2 so that the MAX V device’s IOH specification is not violated. For example, if  
the above device has a maximum IOH of 8 mA, given the I/O clamp diode,  
VIN = VCCIO + 0.7 V = 3.7 V. Given that the maximum supply load of a 5.0-V device  
(VCC) is 5.5 V, calculate value of R2 as follows:  
Equation 5–2.  
5.5 V 3.7 V8 mA 30   
R2 = ----------------------------------------------------------------------------------- = 194   
8 mA  
This analysis assumes worst-case conditions. If your system does not see a wide  
variation in voltage-supply levels, you can adjust these calculations accordingly.  
Because 5.0-V device tolerance in MAX V devices requires the use of the I/O clamp,  
and this clamp is activated only after power-up, 5.0-V signals may not be driven into  
the device until it is configured. The I/O clamp diode is only supported in the  
5M1270Z and 5M2210Z devices’ I/O Bank 3. You must have an external protection  
diode for the other I/O banks for the 5M1270Z and 5M2210Z devices and all the I/O  
pins in the 5M40Z, 5M80Z, 5M160Z, 5M240Z, and 5M570Z devices.  
Recommended Operating Conditions for 5.0-V Compatibility  
As mentioned earlier, a 5.0-V tolerance can be supported with the I/O clamp diode  
enabled with external series/pull-up resistance. To guarantee long term reliability of  
the device’s I/O buffer, there are restrictions on the signal duty cycle that drive the  
MAX V I/O, which is based on the maximum clamp current. Table 5–3 lists the  
maximum signal duty cycle for the 3.3-V VCCIO given a PCI clamp current-handling  
capability.  
Table 5–3. Maximum Signal Duty Cycle  
VIN (V) (1)  
4.0  
ICH (mA) (2)  
5.00  
Max Duty Cycle (%)  
100  
90  
50  
30  
17  
10  
5
4.1  
11.67  
4.2  
18.33  
4.3  
25.00  
4.4  
31.67  
4.5  
38.33  
4.6  
45.00  
Notes to Table 5–3:  
(1) VIN is the voltage at the package pin.  
(2) The ICH is calculated with a 3.3-V VCCIO. A higher VCCIO value will have a lower ICH value with the same VIN.  
December 2010 Altera Corporation  
MAX V Device Handbook