5–2
Chapter 5: Using MAX V Devices in Multi-Voltage Systems
I/O Standards
The Schmitt trigger input option is supported by the 3.3-V and 2.5-V I/O standards.
The I/O Bank 3 also includes the 3.3-V PCI I/O standard interface capability on the
5M1270Z and 5M2210Z devices. Figure 5–1 shows the I/O standards supported by
MAX V devices.
Figure 5–1. I/O Standards Supported by MAX V Devices (Note 1), (2), (3), (4), (5)
I/O Bank 2
I/O Bank 3
also supports
the 3.3-V PCI
I/O Standard
All I/O Banks Support
■ 3.3-V LVTTL/LVCMOS
■ 2.5-V LVTTL/LVCMOS
■ 1.8-V LVTTL/LVCMOS
■ 1.5-V LVCMOS
I/O Bank 1
I/O Bank 3
■ 1.2-V LVCMOS
■ Emulated LVDS output
(LVDS_E_3R)
■ Emulated RSDS output
(RSDS_E_3R)
Individual
Power Bus
I/O Bank 4
Notes to Figure 5–1:
(1) Figure 5–1 is a top view of the silicon die.
(2) Figure 5–1 is a graphical representation only. For the exact pin locations, refer to the pin list and the Quartus® II software.
(3) 5M40Z, 5M80Z, 5M160Z, 5M240Z, and 5M570Z devices only have two I/O banks.
(4) The 3.3-V PCI I/O standard is only supported in 5M1270Z and 5M2210Z devices.
(5) The Schmitt trigger input option for 3.3-V and 2.5-V I/O standards is supported for all I/O pins.
MAX V Device Handbook
December 2010 Altera Corporation
INTEL [ INTEL ]
