Chapter 8: JTAG Boundary-Scan Testing in MAX V Devices
8–11
IEEE Std. 1149.1 BST Operation Control
Figure 8–10 shows the capture, shift, and update phases of EXTESTmode.
Figure 8–10. IEEE Std. 1149.1 BST EXTEST Mode
SDO
PIN_IN
INJ
0
1
D
Input
Q
PIN_OE
OEJ
0
1
0
1
D
Q
D
D
Q
Q
0
1
OE
OE
OUTJ
PIN_OUT
0
1
0
1
D
Q
Pin
Output
Output
Output
Buffer
SHIFT
CLOCK
UPDATE
HIGHZ MODE
Global Signals
Capture
Registers
Update
Registers
SDI
(Capture Phase)
SDO
PIN_IN
INJ
0
1
D
Input
Q
PIN_OE
OEJ
0
1
0
1
D
Q
D
D
Q
Q
0
1
OE
OE
OUTJ
PIN_OUT
0
1
0
1
D
Q
Pin
Output
Output
Output
Buffer
SHIFT
CLOCK
UPDATE
HIGHZ MODE
Global Signals
Capture
Registers
Update
Registers
SDI
(Shift and Update Phase)
December 2010 Altera Corporation
MAX V Device Handbook
INTEL [ INTEL ]
