Document Revision History
Page 63
Document Revision History
Table 64 lists the revision history for this document.
Table 64. Document Revision History (Part 1 of 3)
Date
Version
Changes
■ Added a note in Table 3, Table 4, and Table 5: The power supply value describes the
budget for the DC (static) power supply tolerance and does not include the dynamic
tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic
tolerance requirements.
■ Added a note in Table 19: Differential inputs are powered by VCCPD which requires 2.5 V.
■ Updated "Minimum differential eye opening at the receiver serial input pins" specification
in Table 20.
■ Updated h2f_user2_clk specification for –C6, –C7, and –I7 speed grades in Table 34.
■ Updated description in “HPS PLL Specifications” section.
■ Updated VCO range maximum specification in Table 35.
■ Updated Td and Th specifications in Table 41.
July 2014
3.9
■ Added Th specification in Table 43 and Figure 10.
■ Updated a note in Figure 17, Figure 18, and Figure 20 as follows: Do not leave DCLK
floating after configuration. DCLK is ignored after configuration is complete. It can toggle
high or low if required.
■ Removed “Remote update only in AS mode” specification in Table 54.
■ Added DCLK device initialization clock source specification in Table 56.
■ Added description in “Configuration Files” section: The IOCSR .rbf size is specifically for
the Configuration via Protocol (CvP) feature.
■ Added "Recommended EPCQ Serial Configuration Device" values in Table 57.
■ Removed fMAX_RU_CLK specification in Table 59.
■ Updated VCCRSTCLK_HPS maximum specification in Table 1.
■ Added VCC_AUX_SHARED specification in Table 1.
February 2014
3.8
■ Updated Table 1, Table 3, Table 19, Table 20, Table 23, Table 25, Table 27, Table 34,
Table 44, Table 51, Table 52, Table 55, and Table 61.
■ Removed Preliminary tags for Table 1, Table 2, Table 3, Table 4, Table 5, Table 6, Table 7,
Table 9, Table 12, Table 13, Table 14, Table 15, Table 16, Table 17, Table 18, Table 19,
Table 20, Table 24, Table 25, Table 26, Table 27, Table 28, Table 32, Table 33, Table 49,
Table 50, Table 51, Table 52, Table 53, Table 54, Table 55, Table 57, Table 58, Table 59,
Table 60, and Table 62.
December 2013
November 2013
3.7
3.6
Updated Table 23, Table 30, and Table 31.
■ Added “HPS PLL Specifications”.
■ Added Table 23, Table 35, and Table 36.
■ Updated Table 1, Table 5, Table 11, Table 19, Table 20, Table 21, Table 22, Table 25,
Table 28, Table 34, Table 37, Table 38, Table 39, Table 40, Table 41, Table 42, Table 43,
Table 44, Table 45, Table 46, Table 47, and Table 53.
October 2013
3.5
■ Updated Figure 1, Figure 2, Figure 4, Figure 10, Figure 12, Figure 13, and Figure 16.
■ Removed table: GPIO Pulse Width for Cyclone V Devices.
July 2014 Altera Corporation
Cyclone V Device Datasheet
INTEL [ INTEL ]
