Cyclone V Device Datasheet
CV-51002 | 2018.05.07
Symbol/Description
Condition
Transceiver Speed Grade 5(30)
Transceiver Speed Grade 6
Transceiver Speed Grade 7
Unit
Min
Typ
Max
Min
Typ
VCCE_GXBL supply
—
Max
Min
Typ
VCCE_GXBL supply
—
Max
VICM (AC coupled)
VICM (DC coupled)
—
VCCE_GXBL supply(34)(35)
V
HCSL I/O standard for
the PCIe reference
clock
250
—
550
250
550
250
550
mV
10 Hz
100 Hz
1 KHz
—
—
—
—
—
—
—
—
—
—
—
—
—
–50
–80
—
—
—
—
—
—
—
—
—
—
—
—
—
–50
–80
—
—
—
—
—
—
—
—
—
—
—
—
—
–50
–80
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Ω
Transmitter REFCLK phase
noise(36)
–110
–120
–120
–130
—
–110
–120
–120
–130
—
–110
–120
–120
–130
—
10 KHz
100 KHz
≥1 MHz
—
RREF
2000
±1%
2000
±1%
2000
±1%
(30)
(34)
Transceiver Speed Grade 5 covers specifications for Cyclone V GT and ST devices.
Intel recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V to 1.2 V for Cyclone V GT and ST FPGA systems
which require full compliance to the PCIe Gen2 transmit jitter specification. For more information about the maximum full duplex
channels recommended in Cyclone V GT and ST devices under this condition, refer to the Transceiver Protocol Configurations in
Cyclone V Devices chapter.
(35)
(36)
Intel recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V to 1.2 V for full compliance to CPRI transmit jitter
specification at 4.9152 Gbps (Cyclone V GT and ST devices) and 6.144 Gbps (Cyclone V GT and ST devices only). For more
information about the maximum full duplex channels recommended in Cyclone V GT and ST devices for CPRI 6.144 Gbps, refer to the
Transceiver Protocol Configurations in Cyclone V Devices chapter.
The transmitter REFCLK phase jitter is 30 ps p-p at bit error rate (BER) 10-12
.
Cyclone V Device Datasheet
26
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