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5CSEMA5F31C8N 参数 Datasheet PDF下载

5CSEMA5F31C8N图片预览
型号: 5CSEMA5F31C8N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 85000-Cell, CMOS, PBGA896, ROHS COMPLIANT, FBGA-896]
分类和应用: 可编程逻辑
文件页数/大小: 93 页 / 999 K
品牌: INTEL [ INTEL ]
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Cyclone V Device Datasheet  
CV-51002 | 2018.05.07  
Symbol/Description  
Condition  
Transceiver Speed Grade 5(30)  
Transceiver Speed Grade 6  
Min Typ Max  
±62.5, 100, 125, 200, 250, 300, 500, and 1000  
Transceiver Speed Grade 7  
Unit  
Min  
Typ  
Max  
Min  
Typ  
Max  
Programmable ppm  
detector(46)  
ppm  
Run length  
200  
200  
200  
UI  
Programmable equalization  
AC and DC gain  
AC gain setting = 0  
Refer to CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain for Cyclone V  
GX, GT, SX, and ST Devices and CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and  
DC Gain for Cyclone V GX, GT, SX, and ST Devices diagrams.  
dB  
(47)  
to 3  
DC gain setting = 0  
to 1  
Table 24.  
Transmitter Specifications for Cyclone V GX, GT, SX, and ST Devices  
Symbol/Description  
Condition  
Transceiver Speed Grade 5(30)  
Transceiver Speed Grade 6  
Transceiver Speed Grade 7  
Unit  
Min  
Typ  
Max  
Min  
Typ  
Max  
Min  
Typ  
Max  
Supported I/O standards  
Data rate  
1.5 V PCML  
614  
5000/614  
4(35)  
614  
3125  
614  
2500  
Mbps  
VOCM (AC coupled)  
650  
85  
650  
85  
650  
85  
mV  
Ω
Differential on-chip  
termination resistors  
85-Ω setting  
100-Ω setting  
120-Ω setting  
150-Ω setting  
100  
120  
150  
100  
120  
150  
100  
120  
150  
Ω
Ω
Ω
continued...  
(45)  
tLTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtoref signal goes  
high when the CDR is functioning in the manual mode.  
(46)  
(47)  
The rate matcher supports only up to ±300 parts per million (ppm).  
The Intel Quartus Prime software allows AC gain setting = 3 for design with data rate between 614 Mbps and 1.25 Gbps only.  
Cyclone V Device Datasheet  
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