欢迎访问ic37.com |
会员登录 免费注册
发布采购

5CSEMA5F31C8N 参数 Datasheet PDF下载

5CSEMA5F31C8N图片预览
型号: 5CSEMA5F31C8N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 85000-Cell, CMOS, PBGA896, ROHS COMPLIANT, FBGA-896]
分类和应用: 可编程逻辑
文件页数/大小: 93 页 / 999 K
品牌: INTEL [ INTEL ]
 浏览型号5CSEMA5F31C8N的Datasheet PDF文件第20页浏览型号5CSEMA5F31C8N的Datasheet PDF文件第21页浏览型号5CSEMA5F31C8N的Datasheet PDF文件第22页浏览型号5CSEMA5F31C8N的Datasheet PDF文件第23页浏览型号5CSEMA5F31C8N的Datasheet PDF文件第25页浏览型号5CSEMA5F31C8N的Datasheet PDF文件第26页浏览型号5CSEMA5F31C8N的Datasheet PDF文件第27页浏览型号5CSEMA5F31C8N的Datasheet PDF文件第28页  
Cyclone V Device Datasheet  
CV-51002 | 2018.05.07  
I/O Standard  
VCCIO (V)  
Typ  
VID (mV)(21)  
Condition  
VICM(DC) (V)  
Condition  
VOD (V)(22)  
VOCM (V)(22)(23)  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Typ  
Max  
Min  
Typ  
Max  
LVPECL(29)  
300  
0.60  
DMAX ≤ 700  
Mbps  
1.80  
1.00  
0.05  
0.05  
0.05  
DMAX > 700  
Mbps  
1.60  
1.80  
1.80  
1.80  
SLVS  
2.375  
2.375  
2.375  
2.5  
2.5  
2.5  
2.625  
2.625  
2.625  
100  
100  
100  
VCM = 1.25  
V
Sub-LVDS  
HiSpi  
VCM = 1.25  
V
VCM = 1.25  
V
Related Information  
AN522: Implementing Bus LVDS Interface in Supported Intel Device Families  
Provides more information about BLVDS interface support in Intel devices.  
Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices on page 25  
Provides the specifications for transmitter, receiver, and reference clock I/O pin.  
Switching Characteristics  
This section provides performance characteristics of Cyclone V core and periphery blocks.  
(21)  
(22)  
(23)  
(29)  
The minimum VID value is applicable over the entire common mode range, VCM  
RL range: 90 ≤ RL ≤ 110 Ω.  
.
This applies to default pre-emphasis setting only.  
For optimized LVPECL receiver performance, the receiver voltage input range must be within 0.85 V to 1.75 V for data rate above 700  
Mbps and 0.45 V to 1.95 V for data rate below 700 Mbps.  
Cyclone V Device Datasheet  
24  
Send Feedback  
 
 复制成功!