CV-51002
2015.12.04
80
Remote System Upgrades
Active Serial(93)
Fast Passive Parallel(94)
Variant
Member Code
Width
DCLK (MHz) Minimum Configura‐
tion Time (ms)
Width
DCLK (MHz)
Minimum Configuration Time
(ms)
C2
C4
C5
C6
D5
D6
4
4
4
4
4
4
100
100
100
100
100
100
85
85
16
16
16
16
16
16
125
125
125
125
125
125
17
17
Cyclone V SX
Cyclone V ST
140
140
140
140
28
28
28
28
Related Information
Configuration Files on page 77
Remote System Upgrades
Table 65: Remote System Upgrade Circuitry Timing Specifications for Cyclone V Devices
Parameter
Minimum
250
Unit
ns
(95)
tRU_nCONFIG
(96)
tRU_nRSTIMER
250
ns
Related Information
•
Remote System Upgrade State Machine
Provides more information about configuration reset (RU_CONFIG) signal.
(93)
(94)
(94)
(95)
(96)
DCLK frequency of 100 MHz using external CLKUSR.
Maximum FPGA FPP bandwidth may exceed bandwidth available from some external storage or control logic.
Maximum FPGA FPP bandwidth may exceed bandwidth available from some external storage or control logic.
This is equivalent to strobing the reconfiguration input of the ALTREMOTE_UPDATE IP core high for the minimum timing specification.
This is equivalent to strobing the reset timer input of the ALTREMOTE_UPDATE IP core high for the minimum timing specification.
Cyclone V Device Datasheet
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