CV-51002
2015.12.04
81
User Watchdog Internal Oscillator Frequency Specifications
•
User Watchdog Timer
Provides more information about reset_timer (RU_nRSTIMER) signal.
User Watchdog Internal Oscillator Frequency Specifications
Table 66: User Watchdog Internal Oscillator Frequency Specifications for Cyclone V Devices
Parameter
Minimum
Typical
Maximum
Unit
User watchdog internal oscillator frequency
5.3
7.9
12.5
MHz
I/O Timing
Altera offers two ways to determine I/O timing—the Excel-based I/O timing and the Quartus Prime Timing Analyzer.
Excel-based I/O timing provides pin timing performance for each device density and speed grade. The data is typically used prior to designing the
FPGA to get an estimate of the timing budget as part of the link timing analysis.
The Quartus Prime Timing Analyzer provides a more accurate and precise I/O timing data based on the specifics of the design after you complete
place-and-route.
Related Information
Cyclone V I/O Timing Spreadsheet
Provides the Cyclone V Excel-based I/O timing spreadsheet.
Programmable IOE Delay
Table 67: I/O element (IOE) Programmable Delay for Cyclone V Devices
Fast Model
Slow Model
–C8
Available
Settings
Minimum
Offset(98)
Parameter(97)
Unit
Industrial
Commercial
–C6
–C7
–I7
–A7
D1
32
0
0.508
0.517
0.971
1.187
1.194
1.179
1.160
ns
(97)
You can set this value in the Quartus Prime software by selecting D1, D3, D4, and D5 in the Assignment Name column of Assignment Editor.
Minimum offset does not include the intrinsic delay.
(98)
Cyclone V Device Datasheet
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