CV-51002
2015.12.04
82
Programmable Output Buffer Delay
Fast Model
Slow Model
–C8
Available
Settings
Minimum
Offset(98)
Parameter(97)
Unit
Industrial
Commercial
1.793
–C6
–C7
–I7
–A7
D3
D4
D5
8
0
0
0
1.761
0.510
0.508
3.291
1.180
0.970
4.022
1.187
1.186
3.961
3.999
1.180
1.179
3.929
1.160
1.179
ns
ns
ns
32
32
0.519
1.195
0.517
1.194
Programmable Output Buffer Delay
Table 68: Programmable Output Buffer Delay for Cyclone V Devices
This table lists the delay chain settings that control the rising and falling edge delays of the output buffer.
You can set the programmable output buffer delay in the Quartus Prime software by setting the Output Buffer Delay Control assignment to either
positive, negative, or both edges, with the specific values stated here (in ps) for the Output Buffer Delay assignment.
Symbol
Parameter
Typical
0 (default)
50
Unit
ps
ps
DOUTBUF
Rising and/or falling edge delay
100
ps
150
ps
Glossary
Table 69: Glossary
Term
Definition
Differential I/O standards
Receiver Input Waveforms
(97)
(98)
You can set this value in the Quartus Prime software by selecting D1, D3, D4, and D5 in the Assignment Name column of Assignment Editor.
Minimum offset does not include the intrinsic delay.
Cyclone V Device Datasheet
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