AV-51002
2015.12.16
2-72
User Watchdog Internal Oscillator Frequency Specification
Related Information
•
Configuration, Design Security, and Remote System Upgrades in Arria V Devices
For more information about the reconfiguration input for the ALTREMOTE_UPDATE IP core, refer to the “User Watchdog Timer” section.
Configuration, Design Security, and Remote System Upgrades in Arria V Devices
For more information about the reset_timerinput for the ALTREMOTE_UPDATE IP core, refer to the “Remote System Upgrade State
Machine” section.
•
User Watchdog Internal Oscillator Frequency Specification
Table 2-65: User Watchdog Internal Oscillator Frequency Specifications
Minimum
Typical
Maximum
Unit
5.3
7.9
12.5
MHz
I/O Timing
Altera offers two ways to determine I/O timing—the Excel-based I/O Timing and the Quartus II Timing Analyzer.
Excel-based I/O timing provides pin timing performance for each device density and speed grade. The data is typically used prior to designing the
FPGA to get an estimate of the timing budget as part of the link timing analysis.
The Quartus II Timing Analyzer provides a more accurate and precise I/O timing data based on the specifics of the design after you complete
place-and-route.
Related Information
Arria V Devices Documentation page
For the Excel-based I/O Timing spreadsheet
(225)
(226)
This is equivalent to strobing the reconfiguration input of the ALTREMOTE_UPDATE IP core high for the minimum timing specification. For more
information, refer to the “Remote System Upgrade State Machine” section in the Configuration, Design Security, and Remote System Upgrades in
Arria V Devices chapter.
This is equivalent to strobing the reset_timer input of the ALTREMOTE_UPDATE IP core high for the minimum timing specification. For more
information, refer to the “User Watchdog Timer” section in the Configuration, Design Security, and Remote System Upgrades in Arria V Devices
chapter.
Arria V GZ Device Datasheet
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