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5AGXMA1D6F27C6N 参数 Datasheet PDF下载

5AGXMA1D6F27C6N图片预览
型号: 5AGXMA1D6F27C6N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 500MHz, 75000-Cell, CMOS, PBGA672, ROHS COMPLIANT, FBGA-672]
分类和应用: 可编程逻辑
文件页数/大小: 182 页 / 2239 K
品牌: INTEL [ INTEL ]
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AV-51002  
2015.12.16  
2-69  
Passive Serial Configuration Timing  
Table 2-60: PS Timing Parameters for Arria V GZ Devices  
Symbol  
tCF2CD  
tCF2ST0  
tCFG  
Parameter  
Minimum  
Maximum  
600  
Unit  
ns  
ns  
μs  
nCONFIGlow to CONF_DONElow  
nCONFIGlow to nSTATUSlow  
nCONFIGlow pulse width  
600  
2
tSTATUS  
tCF2ST1  
nSTATUSlow pulse width  
268  
1,506 (216)  
1,506 (217)  
μs  
nCONFIGhigh to nSTATUShigh  
μs  
tCF2CK  
nCONFIGhigh to first rising edge on DCLK  
1,506  
μs  
(218)  
(218)  
tST2CK  
tDSU  
nSTATUShigh to first rising edge of DCLK  
DATA[] setup time before rising edge on DCLK  
DATA[] hold time after rising edge on DCLK  
DCLKhigh time  
2
μs  
ns  
ns  
s
5.5  
tDH  
0
0.45 × 1/fMAX  
0.45 × 1/fMAX  
1/fMAX  
tCH  
tCL  
DCLKlow time  
s
tCLK  
DCLKperiod  
s
fMAX  
tCD2UM  
tCD2CU  
DCLKfrequency  
CONF_DONEhigh to user mode (219)  
125  
437  
MHz  
μs  
175  
CONF_DONEhigh to CLKUSRenabled  
4 × maximum DCLK  
period  
tCD2UMC CONF_DONEhigh to user mode with CLKUSRoption on  
tCD2CU + (17,408 ×  
CLKUSRperiod) (220)  
(216)  
This value is applicable if you do not delay configuration by extending the nCONFIGor nSTATUSlow pulse width.  
This value is applicable if you do not delay configuration by externally holding the nSTATUSlow.  
(217)  
(218)  
(219)  
If nSTATUSis monitored, follow the tST2CK specification. If nSTATUSis not monitored, follow the tCF2CK specification.  
The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for initializing the device.  
Arria V GZ Device Datasheet  
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Altera Corporation  
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