Electrical Specifications
3.
4.
Refer to
for processor VCC information.
The load lines specify voltage limits at the die measured at the VCC_DIE_SENSE and VSS_DIE_SENSE
lands and at the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Voltage regulation feedback for voltage
regulator circuits must also be taken from processor VCC_DIE_SENSE and VSS_DIE_SENSE lands and
VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Please refer to the appropriate platform design guide for
details on VR implementation.
Table 2-12. BSEL[2:0], VID[5:0] Signal Group DC Specifications
Symbol
R
ON
I
OL
I
OH
V
TOL
Parameter
BSEL[2:0], VID[5:0]
Buffer On Resistance
Output Low Current
Output High Current
Voltage Tolerance
Min
N/A
N/A
N/A
0.95 * V
TT
Max
120
2.4
460
1.05 * V
TT
Units
Notes
1
2
2, 3
2, 3
4
Ω
mA
µA
V
Notes:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
These parameters are based on design characterization and are not tested.
3.
I
OL
is measured at 0.10*V
TT
, I
OH
is measured at 0.90*V
TT
.
4.
Please refer to the appropriate platform design guide for implementation details.
Table 2-13. AGTL+ Signal Group DC Specifications
Symbol
V
IL
V
IH
V
OH
I
OL
I
LI
I
LO
R
ON
Parameter
Input Low Voltage
Input High Voltage
Output High Voltage
Output Low Current
Input Leakage Current
Output Leakage Current
Buffer On Resistance
Min
0.0
GTLREF + (0.10 * V
TT
)
0.90 * V
TT
N/A
N/A
N/A
7
Max
GTLREF - (0.10 * V
TT
)
V
TT
V
TT
V
TT
/
(0.50 * R
TT_MIN
+ R
ON_MIN
)
± 200
± 200
11
Unit
V
V
V
mA
µA
µA
Notes
1
2
3, 4
4
4
5, 6
5, 6
7
Ω
Notes:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
V
IL
is defined as the voltage range at a receiving agent that will be interpreted as an electrical low value.
3.
V
IH
is defined as the voltage range at a receiving agent that will be interpreted as an electrical high value.
4.
V
IH
and V
OH
may experience excursions above V
TT
. However, input signal drivers must comply with the
signal quality specifications in
5.
Leakage to V
SS
with land held at V
TT
.
6.
Leakage to V
TT
with land held at 300 mV.
7.
This parameter is based on design characterization and is not tested
Table 2-14. PWRGOOD Input and TAP Signal Group DC Specifications (Sheet 1 of 2)
Symbol
V
HYS
V
t+
Parameter
Input Hysteresis
PWRGOOD Input Low to
High Threshold Voltage
TAP Input Low to High
Threshold Voltage
V
t-
PWRGOOD Input High to
Low Threshold Voltage
TAP Input High to Low
Threshold Voltage
V
OH
Output High Voltage
Min
120
0.5 * (V
TT
+ V
HYS_MIN
+
0.24)
0.5 * (V
TT
+ V
HYS_MIN
)
0.4 * V
TT
0.5 * (V
TT
-V
HYS_MAX
)
N/A
Max
396
0.5 * (V
TT
+ V
HYS_MAX
+
0.24)
0.5 * (V
TT
+ V
HYS_MAX
)
0.6 * V
TT
0.5 * (V
TT
- V
HYS_MIN
)
V
TT
Unit
mV
V
V
V
V
V
4
Notes
1,
2
3
30
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
INTEL [ INTEL CORPORATION ]
