Electrical Specifications
Table 2-10. Voltage and Current Specifications (Sheet 2 of 2)
Symbol
I
CC_RESET
Parameter
I
CC_RESET
for Dual-Core Intel Xeon
Processor 5000 series with multiple
VID
(1066 MHz)
I
CC_RESET
for Dual-Core Intel Xeon
Processor 5063 (MV) with multiple
VID
Steady-state FSB Termination
Current
Power-up FSB Termination Current
Thermal Design Current (TDC) for
Dual-Core Intel Xeon Processor
5000 series
(667 MHz)
Thermal Design Current (TDC) for
Dual-Core Intel Xeon Processor
5000 series
(1066 MHz)
Thermal Design Current (TDC) for
Dual-Core Intel Xeon Processor
5063 (MV)
DC current that may be drawn
from V
TTOUT
per land
I
CC
for PLL power lands
I
CC
for PLL power lands
I
CC
for GTLREF
I
CC
during active thermal control
circuit (TCC) for Dual-Core Intel
Xeon Processor 5000 series
I
CC
during active thermal control
circuit (TCC) for Dual-Core Intel
Xeon Processor 5063 (MV)
I
CC
Stop-Grant for Dual-Core Intel
Xeon Processor 5000 series
(667
MHz)
I
CC
Stop-Grant for Dual-Core Intel
Xeon Processor 5000 series
(1066
MHz)
I
CC
Stop-Grant for Dual-Core Intel
Xeon Processor 5063 (MV)
Min
Typ
Max
150
Unit
A
Notes
1,13
18
I
CC_RESET
115
A
18
I
TT
I
TT_POWER-UP
I
CC_TDC
6.1
8.0
100
A
A
A
16
19
6,15
I
CC_TDC
130
A
6,15
I
CC_TDC
100
A
6,15
I
CC_VTTOUT
I
CC_VCCA
I
CC_VCCIOPLL
I
CC_GTLREF
I
TCC
580
120
100
200
150
mA
mA
mA
µA
A
17
8
8
9
I
TCC
115
A
I
SGNT
50
A
7
I
SGNT
60
A
7
I
SGNT
40
A
7
Notes:
1.
Unless otherwise noted, all specifications in this table apply to all processors and are based on final silicon
validation/characterization.
2.
These voltages are targets only. A variable voltage source should exist on systems in the event that a
different voltage is required. See
for more information.
3.
The voltage specification requirements are measured across the VCC_DIE_SENSE and VSS_DIE_SENSE
lands and across the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands with a 100 MHz bandwidth
oscilloscope, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length of
ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled
in the scope probe.
4.
The processor must not be subjected to any static V
CC
level that exceeds the V
CC_MAX
associated with any
particular current. Failure to adhere to this specification can shorten processor lifetime.
5.
I
CC_MAX
is specified at V
CC_MAX
. The processor is capable of drawing I
CC_MAX
for up to 10 ms. Refer to
and
for further details on the average processor current draw over various time
durations.
6.
FMB is the flexible motherboard guideline. These guidelines are for estimation purposes only.
7.
The current specified is also for HALT and Enhanced HALT State.
8.
These specifications apply to the PLL power lands VCCA, VCCIOPLL, and VSSA. See
for
details. These parameters are based on design characterization and are not tested.
9.
This specification represents the total current for GTLREF_DATA and GTLREF_ADD per core.
10. V
TT
must be provided via a separate voltage source and must not be connected to V
CC
. This specification is
measured at the land.
26
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
INTEL [ INTEL CORPORATION ]
