Electrical Specifications
Table 2-14. PWRGOOD Input and TAP Signal Group DC Specifications (Sheet 2 of 2)
Symbol
I
LI
I
LO
R
ON
Parameter
Input Leakage Current
Output Leakage Current
Buffer On Resistance
Min
N/A
N/A
7
Max
± 200
± 200
11
Unit
µA
µA
Notes
1,
2
Ω
5
Notes:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
All outputs are open drain.
3.
V
HYS
represents the amount of hysteresis, nominally centered about 0.5 * V
TT
for all PWRGOOD and TAP
inputs.
4.
PWRGOOD input and the TAP signal group must meet system signal quality specification in
5.
The maximum output current is based on maximum current handling capability of the buffer and is not
specified into the test load.
Table 2-15. GTL+ Asynchronous and AGTL+ Asynchronous Signal Group
DC Specifications
Symbol
V
IL
V
IH
V
OH
I
OL
I
LI
I
LO
R
ON
Parameter
Input Low Voltage
Input High Voltage
Output High Voltage
Output Low Current
Input Leakage Current
Output Leakage
Current
Buffer On Resistance
Min
0.0
(0.5 * V
TT
) + (0.10 * V
TT
)
0.90*V
TT
-
N/A
N/A
7
Max
(0.5 * V
TT
) - (0.10 * V
TT
)
V
TT
V
TT
V
TT
/
[(0.50*R
TT_MIN
)+(R
ON_MIN
)]
± 200
± 200
11
Unit
V
V
V
A
µA
µA
Notes
1
3, 11
4, 5, 7,
11
2, 5, 7
8
9
10
6
Ω
Notes:
1.Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.All outputs are open drain.
3.V
IL
is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.
4.V
IH
is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.
5.V
IH
and V
OH
may experience excursions above V
TT
. However, input signal drivers must comply with the signal
quality specifications in
6.Refer to the processor HSPICE* I/O Buffer Models for I/V characteristics.
7.The V
TT
referred to in these specifications refers to instantaneous V
TT
.
8.The maximum output current is based on maximum current handling capability of the buffer and is not
specified into the test load.
9.Leakage to V
SS
with land held at V
TT
.
10.Leakage to V
TT
with land held at 300 mV.
11.LINT0/INTR and LINT1/NMI use GTLREF_ADD as a reference voltage. For these two signals V
IH
=
GTLREF_ADD + (0.10 * V
TT
) and V
IL
= GTLREF_ADD - (0.10 * V
TT
).
Table 2-16. VTTPWRGD DC Specifications
Symbol
V
IL
V
IH
Parameter
Input Low Voltage
Input High Voltage
Min
0.0
0.90
Max
0.30
V
TT
Unit
V
V
2.12.1
V
CC
Overshoot Specification
The Dual-Core Intel Xeon Processor 5000 series can tolerate short transient overshoot
events where V
CC
exceeds the VID voltage when transitioning from a high-to-low
current load condition. This overshoot cannot exceed VID + V
OS_MAX
(V
OS_MAX
is the
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
31
INTEL [ INTEL CORPORATION ]
