Introduction
1
Introduction
The Intel® Celeron® M processor based on 90 nm process technology is a high-
performance, low-power mobile processor with several enhancements over previous
mobile Celeron processors.
Throughout this document, the term Celeron M processor signifies Intel Celeron M
processor based on 90 nm technology.
This document contains specification for the Celeron M processor 390, 380, 370, 360J,
360, 350J, 350
Δ
and the Celeron M processor Ultra Low Voltage 383, 373, 353
Δ
.
Note:
Δ
Intel processor numbers are not a measure of performance. Processor numbers
differentiate features within each processor family, not across different processor
families. See www.intel.com/products/processor_number for details.
The following list provides some of the key features on this processor:
• Manufactured on Intel’s advanced 90 nanometer process technology with copper
interconnect.
• Supports Intel Architecture with Dynamic Execution
• On-die, primary 32-KB instruction cache and 32-KB write-back data cache
• On-die 1-MB (512-KB for Celeron M processor Ultra Low Voltage 373 and 353)
second level cache with Advanced Transfer Cache Architecture, 8-way set
associativity and ECC (Error Correcting Code) Support.
• Data Prefetch Logic
• Streaming SIMD extensions 2 (SSE2)
• 400-MHz, source-synchronous front side bus (FSB)
• Micro-FCPGA and Micro-FCBGA (ULV parts available only in Micro-FCBGA)
packaging technologies (including lead free technology for the Micro-FCBGA
package for Celeron M processors 390, 380, 370, 383, 373, and 353).
• Execute Disable Bit support for enhanced security (available on processors with
CPU Signature=06D8h and recommended for implementation on Intel® 915/910
Express Chipset-based platforms only)
The Celeron M processor maintains support for MMX™ technology and Internet
Streaming SIMD instructions and full compatibility with IA-32 software. The on-die,
32-KB Level 1 instruction and data caches and the 1-MB (512-KB for Celeron M
processor Ultra Low Voltage 373 and 353) Level 2 cache with advanced transfer cache
architecture enable significant performance improvement over existing mobile
processors. The processor’s data prefetch logic speculatively fetches data to the L2
cache before an L1 cache requests occurs, resulting in reduced bus cycle penalties and
improved performance.
The streaming SIMD extensions 2 (SSE2) enable break-through levels of performance
in multimedia applications including 3-D graphics, video decoding/encoding, and
speech recognition. The new packed double-precision floating-point instructions
enhance performance for applications that require greater range and precision,
including scientific and engineering applications and advanced 3-D geometry
techniques, such as ray tracing.
The Celeron M processor’s 400-MHz FSB utilizes a split-transaction, deferred reply
protocol. The 400-MHz FSB uses source-synchronous transfer (SST) of address and
data to improve performance by transferring data four times per bus clock (4X data
Datasheet
7
INTEL [ INTEL CORPORATION ]
